Searched refs:MCF_IPSBAR (Results 1 – 5 of 5) sorted by relevance
24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */72 #define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */73 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */74 #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */75 #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */76 #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */79 #define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */80 #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */81 #define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */[all …]
24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */63 #define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */64 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */65 #define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */66 #define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */67 #define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */72 #define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100)73 #define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140)74 #define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180)[all …]
24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */63 #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */64 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */65 #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */66 #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */67 #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */72 #define MCF_RCR (MCF_IPSBAR + 0x110000)73 #define MCF_RSR (MCF_IPSBAR + 0x110001)81 #define MCFUART_BASE0 (MCF_IPSBAR + 0x200)[all …]
46 #define MCF_IPSBAR CONFIG_IPSBAR macro
23 #define DTMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x400)24 #define DTXMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x402)25 #define DTER0 (MCF_IPSBAR + DMA_TIMER_0 + 0x403)26 #define DTRR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x404)27 #define DTCR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x408)28 #define DTCN0 (MCF_IPSBAR + DMA_TIMER_0 + 0x40c)