1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */ 3 4 #ifndef __HALDMOUTSRC_H__ 5 #define __HALDMOUTSRC_H__ 6 7 struct rtw_dig { 8 u8 PreIGValue; 9 u8 CurIGValue; 10 u8 BackupIGValue; 11 12 u8 rx_gain_range_max; 13 u8 rx_gain_range_min; 14 15 u8 CurCCK_CCAThres; 16 17 u8 LargeFAHit; 18 u8 ForbiddenIGI; 19 u32 Recover_cnt; 20 21 u8 DIG_Dynamic_MIN_0; 22 bool bMediaConnect_0; 23 24 u32 AntDiv_RSSI_max; 25 u32 RSSI_max; 26 }; 27 28 struct rtl_ps { 29 u8 pre_rf_state; 30 u8 cur_rf_state; 31 u8 initialize; 32 u32 reg_874; 33 u32 reg_c70; 34 u32 reg_85c; 35 u32 reg_a74; 36 37 }; 38 39 struct false_alarm_stats { 40 u32 Cnt_Parity_Fail; 41 u32 Cnt_Rate_Illegal; 42 u32 Cnt_Crc8_fail; 43 u32 Cnt_Mcs_fail; 44 u32 Cnt_Ofdm_fail; 45 u32 Cnt_Cck_fail; 46 u32 Cnt_all; 47 u32 Cnt_Fast_Fsync; 48 u32 Cnt_SB_Search_fail; 49 u32 Cnt_OFDM_CCA; 50 u32 Cnt_CCK_CCA; 51 u32 Cnt_CCA_all; 52 u32 Cnt_BW_USC; /* Gary */ 53 u32 Cnt_BW_LSC; /* Gary */ 54 }; 55 56 #define ODM_ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 57 58 struct sw_ant_switch { 59 u8 CurAntenna; 60 u8 SWAS_NoLink_State; /* Before link Antenna Switch check */ 61 u8 RxIdleAnt; 62 }; 63 64 struct edca_turbo { 65 bool bCurrentTurboEDCA; 66 bool bIsCurRDLState; 67 u32 prv_traffic_idx; /* edca turbo */ 68 }; 69 70 struct odm_rate_adapt { 71 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 72 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 73 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 74 u32 LastRATR; /* RATR Register Content */ 75 }; 76 77 #define IQK_MAC_REG_NUM 4 78 #define IQK_ADDA_REG_NUM 16 79 #define IQK_BB_REG_NUM 9 80 #define HP_THERMAL_NUM 8 81 82 #define AVG_THERMAL_NUM 8 83 #define IQK_Matrix_REG_NUM 8 84 85 struct odm_phy_dbg_info { 86 /* ODM Write,debug info */ 87 s8 RxSNRdB[MAX_PATH_NUM_92CS]; 88 u64 NumQryPhyStatus; 89 /* Others */ 90 s32 RxEVM[MAX_PATH_NUM_92CS]; 91 }; 92 93 struct odm_per_pkt_info { 94 s8 Rate; 95 u8 StationID; 96 bool bPacketMatchBSSID; 97 bool bPacketToSelf; 98 bool bPacketBeacon; 99 }; 100 101 /* 2011/10/20 MH Define Common info enum for all team. */ 102 103 enum odm_common_info_def { 104 /* Fixed value: */ 105 106 /* HOOK BEFORE REG INIT----------- */ 107 ODM_CMNINFO_MP_TEST_CHIP, 108 /* HOOK BEFORE REG INIT----------- */ 109 110 /* CALL BY VALUE------------- */ 111 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 112 /* CALL BY VALUE-------------*/ 113 }; 114 115 enum odm_ability_def { 116 /* BB ODM section BIT 0-15 */ 117 ODM_BB_RSSI_MONITOR = BIT(4), 118 ODM_BB_ANT_DIV = BIT(6), 119 ODM_BB_PWR_TRA = BIT(8), 120 }; 121 122 # define ODM_ITRF_USB 0x2 123 124 /* ODM_CMNINFO_WM_MODE */ 125 enum odm_wireless_mode { 126 ODM_WM_UNKNOW = 0x0, 127 ODM_WM_B = BIT(0), 128 ODM_WM_G = BIT(1), 129 ODM_WM_N24G = BIT(3), 130 ODM_WM_AUTO = BIT(5), 131 }; 132 133 struct odm_ra_info { 134 u8 RateID; 135 u32 RateMask; 136 u32 RAUseRate; 137 u8 RateSGI; 138 u8 RssiStaRA; 139 u8 PreRssiStaRA; 140 u8 SGIEnable; 141 u8 DecisionRate; 142 u8 PreRate; 143 u8 HighestRate; 144 u8 LowestRate; 145 u32 NscUp; 146 u32 NscDown; 147 u16 RTY[5]; 148 u32 TOTAL; 149 u16 DROP; 150 u8 Active; 151 u16 RptTime; 152 u8 RAWaitingCounter; 153 u8 RAPendingCounter; 154 u8 PTActive; /* on or off */ 155 u8 PTTryState; /* 0 trying state, 1 for decision state */ 156 u8 PTStage; /* 0~6 */ 157 u8 PTStopCount; /* Stop PT counter */ 158 u8 PTPreRate; /* if rate change do PT */ 159 u8 PTPreRssi; /* if RSSI change 5% do PT */ 160 u8 PTModeSS; /* decide whitch rate should do PT */ 161 u8 RAstage; /* StageRA, decide how many times RA will be done 162 * between PT */ 163 u8 PTSmoothFactor; 164 }; 165 166 struct ijk_matrix_regs_set { 167 bool bIQKDone; 168 s32 Value[1][IQK_Matrix_REG_NUM]; 169 }; 170 171 struct odm_rf_cal { 172 /* for tx power tracking */ 173 u32 RegA24; /* for TempCCK */ 174 s32 RegE94; 175 s32 RegE9C; 176 s32 RegEB4; 177 s32 RegEBC; 178 179 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking 180 * as default */ 181 u8 TM_Trigger; 182 u8 InternalPA5G[2]; /* pathA / pathB */ 183 184 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, 185 * and 1 for RFIC1 */ 186 u8 ThermalValue; 187 u8 ThermalValue_LCK; 188 u8 ThermalValue_IQK; 189 u8 ThermalValue_DPK; 190 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 191 u8 ThermalValue_AVG_index; 192 u8 ThermalValue_RxGain; 193 u8 ThermalValue_Crystal; 194 u8 ThermalValue_DPKstore; 195 u8 ThermalValue_DPKtrack; 196 bool TxPowerTrackingInProgress; 197 bool bDPKenable; 198 199 bool bReloadtxpowerindex; 200 u8 bRfPiEnable; 201 202 u8 CCK_index; 203 u8 OFDM_index; 204 bool bDoneTxpower; 205 206 u8 ThermalValue_HP[HP_THERMAL_NUM]; 207 u8 ThermalValue_HP_index; 208 struct ijk_matrix_regs_set IQKMatrixRegSetting; 209 210 u8 Delta_IQK; 211 u8 Delta_LCK; 212 213 /* for IQK */ 214 u32 RegC04; 215 u32 Reg874; 216 u32 RegC08; 217 u32 RegB68; 218 u32 RegB6C; 219 u32 Reg870; 220 u32 Reg860; 221 u32 Reg864; 222 223 bool bIQKInitialized; 224 bool bAntennaDetected; 225 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 226 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 227 u32 IQK_BB_backup_recover[9]; 228 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 229 230 /* for APK */ 231 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 232 u8 bAPKdone; 233 u8 bAPKThermalMeterIgnore; 234 u8 bDPdone; 235 u8 bDPPathAOK; 236 u8 bDPPathBOK; 237 }; 238 239 /* ODM Dynamic common info value definition */ 240 241 struct fast_ant_train { 242 u8 antsel_rx_keep_0; 243 u8 antsel_rx_keep_1; 244 u8 antsel_rx_keep_2; 245 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 246 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 247 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 248 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 249 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 250 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 251 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 252 u8 RxIdleAnt; 253 bool bBecomeLinked; 254 }; 255 256 enum ant_div_type { 257 NO_ANTDIV = 0xFF, 258 CG_TRX_HW_ANTDIV = 0x01, 259 CGCS_RX_HW_ANTDIV = 0x02, 260 FIXED_HW_ANTDIV = 0x03, 261 CG_TRX_SMART_ANTDIV = 0x04, 262 }; 263 264 /* Copy from SD4 defined structure. We use to support PHY DM integration. */ 265 struct odm_dm_struct { 266 struct adapter *Adapter; /* For CE/NIC team */ 267 268 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 269 bool bCckHighPower; 270 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 271 u8 ControlChannel; 272 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 273 274 /* 1 COMMON INFORMATION */ 275 /* Init Value */ 276 /* HOOK BEFORE REG INIT----------- */ 277 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ �K�K = 1/2/3/�K */ 278 u32 SupportAbility; 279 280 u32 BK_SupportAbility; 281 u8 AntDivType; 282 /* HOOK BEFORE REG INIT----------- */ 283 284 /* Dynamic Value */ 285 /* POINTER REFERENCE----------- */ 286 /* Wireless mode B/G/A/N = BIT(0)/BIT(1)/BIT(2)/BIT(3) */ 287 u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */ 288 /* Secondary channel offset don't_care/below/above = 0/1/2 */ 289 u8 *pSecChOffset; 290 /* BW info 20M/40M/80M = 0/1/2 */ 291 enum ht_channel_width *pBandWidth; 292 /* Central channel location Ch1/Ch2/.... */ 293 u8 *pChannel; /* central channel number */ 294 295 /* Common info for Status */ 296 bool *pbScanInProcess; 297 bool *pbPowerSaving; 298 /* POINTER REFERENCE----------- */ 299 /* */ 300 /* CALL BY VALUE------------- */ 301 bool bLinked; 302 u8 RSSI_Min; 303 bool bIsMPChip; 304 bool bOneEntryOnly; 305 /* CALL BY VALUE------------- */ 306 307 /* 2 Define STA info. */ 308 /* _ODM_STA_INFO */ 309 /* For MP, we need to reduce one array pointer for default port.?? */ 310 struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 311 312 u16 CurrminRptTime; 313 struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as 314 * array index. STA MacID=0, 315 * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */ 316 317 /* Latest packet phy info (ODM write) */ 318 struct odm_phy_dbg_info PhyDbgInfo; 319 320 /* ODM Structure */ 321 struct fast_ant_train DM_FatTable; 322 struct rtw_dig DM_DigTable; 323 struct rtl_ps DM_PSTable; 324 struct false_alarm_stats FalseAlmCnt; 325 struct sw_ant_switch DM_SWAT_Table; 326 327 struct edca_turbo DM_EDCA_Table; 328 329 /* PSD */ 330 bool bDMInitialGainEnable; 331 332 struct odm_rate_adapt RateAdaptive; 333 334 struct odm_rf_cal RFCalibrateInfo; 335 336 /* TX power tracking */ 337 u8 BbSwingIdxOfdm; 338 u8 BbSwingIdxOfdmCurrent; 339 u8 BbSwingIdxOfdmBase; 340 bool BbSwingFlagOfdm; 341 u8 BbSwingIdxCck; 342 u8 BbSwingIdxCckCurrent; 343 u8 BbSwingIdxCckBase; 344 bool BbSwingFlagCck; 345 }; 346 347 enum odm_bb_config_type { 348 CONFIG_BB_PHY_REG, 349 CONFIG_BB_AGC_TAB, 350 CONFIG_BB_AGC_TAB_2G, 351 CONFIG_BB_PHY_REG_PG, 352 }; 353 354 #define DM_DIG_MAX_NIC 0x4e 355 #define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */ 356 357 #define DM_DIG_MAX_AP 0x32 358 359 /* vivi 92c&92d has different definition, 20110504 */ 360 /* this is for 92c */ 361 #define DM_DIG_FA_TH0 0x200/* 0x20 */ 362 #define DM_DIG_FA_TH1 0x300/* 0x100 */ 363 #define DM_DIG_FA_TH2 0x400/* 0x200 */ 364 365 /* 3=========================================================== */ 366 /* 3 Rate Adaptive */ 367 /* 3=========================================================== */ 368 #define DM_RATR_STA_INIT 0 369 #define DM_RATR_STA_HIGH 1 370 #define DM_RATR_STA_MIDDLE 2 371 #define DM_RATR_STA_LOW 3 372 373 /* 3=========================================================== */ 374 /* 3 BB Power Save */ 375 /* 3=========================================================== */ 376 377 enum dm_rf { 378 RF_Save = 0, 379 RF_Normal = 1, 380 RF_MAX = 2, 381 }; 382 383 /* 3=========================================================== */ 384 /* 3 Antenna Diversity */ 385 /* 3=========================================================== */ 386 enum dm_swas { 387 Antenna_A = 1, 388 Antenna_B = 2, 389 Antenna_MAX = 3, 390 }; 391 392 /* Extern Global Variables. */ 393 #define OFDM_TABLE_SIZE_92D 43 394 #define CCK_TABLE_SIZE 33 395 396 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D]; 397 extern u8 cck_swing_table[CCK_TABLE_SIZE][8]; 398 399 /* check Sta pointer valid or not */ 400 #define IS_STA_VALID(pSta) (pSta) 401 402 void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI); 403 void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres); 404 405 void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal); 406 407 void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm); 408 409 bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, 410 bool bForceUpdate, u8 *pRATRState); 411 412 u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, 413 u32 ra_mask, u8 rssi_level); 414 415 void ODM_DMInit(struct odm_dm_struct *pDM_Odm); 416 417 void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm); 418 419 void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, 420 enum odm_common_info_def CmnInfo, u32 Value); 421 422 #endif 423