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Searched refs:LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT (Results 1 – 12 of 12) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_sh_mask.h7620 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x00000010 macro
Ddce_8_0_sh_mask.h3190 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 macro
Ddce_10_0_sh_mask.h3112 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 macro
Ddce_11_0_sh_mask.h3182 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 macro
Ddce_11_2_sh_mask.h3430 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 macro
Ddce_12_0_sh_mask.h9251 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT … macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_sh_mask.h21248 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT … macro
Ddcn_1_0_sh_mask.h40002 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT … macro
Ddcn_2_1_0_sh_mask.h43236 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT … macro
Ddcn_3_0_2_sh_mask.h42518 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT … macro
Ddcn_2_0_0_sh_mask.h48745 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT … macro
Ddcn_3_0_0_sh_mask.h49113 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT … macro