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/linux-6.1.9/arch/mips/cavium-octeon/
DKconfig30 bool "Lock often used kernel code in the L2"
33 Enable locking parts of the kernel into the L2 cache.
36 bool "Lock the TLB handler in L2"
40 Lock the low level TLB fast path into L2.
43 bool "Lock the exception handler in L2"
47 Lock the low level exception handler into L2.
50 bool "Lock the interrupt handler in L2"
54 Lock the low level interrupt handler into L2.
57 bool "Lock the 2nd level interrupt handler in L2"
61 Lock the 2nd level interrupt handler in L2.
[all …]
/linux-6.1.9/Documentation/devicetree/bindings/powerpc/fsl/
Dl2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
42 - reg : Address and size of L2 cache controller registers
43 - cache-size : Size of the entire L2 cache
44 - interrupts : Error interrupt of L2 controller
45 - cache-line-size : Size of L2 cache lines
49 L2: l2-cache-controller@20000 {
53 cache-size = <0x40000>; // L2,256K
/linux-6.1.9/arch/arc/kernel/
Dentry-compact.S152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
154 ; This is to avoid a potential L1-L2-L1 scenario
156 ; -L2 interrupts L1 (before L1 ISR could run)
159 ; Returns from L2 context fine
160 ; But both L1 and L2 re-enabled, so another L1 can be taken
165 ; L2 interrupting L1 implies both L2 and L1 active
170 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
209 ; out of the L2 interrupt context (drop to pure kernel mode) and jump
335 ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
350 ; However the context returning might not have taken L2 intr itself
[all …]
/linux-6.1.9/security/apparmor/include/
Dperms.h122 #define xcheck_ns_labels(L1, L2, FN, args...) \ argument
125 fn_for_each((L1), __p1, FN(__p1, (L2), args)); \
129 #define xcheck_labels_profiles(L1, L2, FN, args...) \ argument
130 xcheck_ns_labels((L1), (L2), xcheck_ns_profile_label, (FN), args)
132 #define xcheck_labels(L1, L2, P, FN1, FN2) \ argument
133 xcheck(fn_for_each((L1), (P), (FN1)), fn_for_each((L2), (P), (FN2)))
Dlabel.h163 #define next_comb(I, L1, L2) \ argument
166 if ((I).j >= (L2)->size) { \
174 #define label_for_each_comb(I, L1, L2, P1, P2) \ argument
176 ((P1) = (L1)->vec[(I).i]) && ((P2) = (L2)->vec[(I).j]); \
177 (I) = next_comb(I, L1, L2))
179 #define fn_for_each_comb(L1, L2, P1, P2, FN) \ argument
183 label_for_each_comb(i, (L1), (L2), (P1), (P2)) { \
243 #define fn_for_each2_XXX(L1, L2, P, FN, ...) \ argument
247 label_for_each ## __VA_ARGS__(i, (L1), (L2), (P)) { \
253 #define fn_for_each_in_merge(L1, L2, P, FN) \ argument
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/linux-6.1.9/Documentation/devicetree/bindings/arm/
Dl2c2x0.yaml7 title: ARM L2 Cache Controller
15 implementations of the L2 cache controller have compatible programming
21 Note 1: The description in this document doesn't apply to integrated L2
23 integrated L2 controllers are assumed to be all preconfigured by
40 # offset needs to be added to the address before passing down to the L2
45 # maintenance operations on L1 are broadcasted to the L2 and L2
124 description: If present then L2 is forced to Write through mode
166 description: enable parity checking on the L2 cache (L220 or PL310).
170 description: disable parity checking on the L2 cache (L220 or PL310).
174 description: enable ECC protection on the L2 cache
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/linux-6.1.9/arch/arm/boot/dts/
Dhighbank.dts25 next-level-cache = <&L2>;
44 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
82 next-level-cache = <&L2>;
135 L2: cache-controller { label
Dvexpress-v2p-ca9.dts42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
164 L2: cache-controller@1e00a000 { label
225 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
270 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
284 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
Darm-realview-eb-a9mp.dts42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
Darm-realview-eb-11mp.dts46 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
60 next-level-cache = <&L2>;
67 next-level-cache = <&L2>;
Dvf610.dtsi8 next-level-cache = <&L2>;
12 L2: cache-controller@40006000 { label
Dbcm4708.dtsi31 next-level-cache = <&L2>;
38 next-level-cache = <&L2>;
/linux-6.1.9/Documentation/virt/kvm/x86/
Drunning-nested-guests.rst14 | L2 | | L2 |
36 - L2 – level-2 guest; a VM running on L1, this is the "nested guest"
45 metal, running the LPAR hypervisor), L1 (host hypervisor), L2
49 L1, and L2) for all architectures; and will largely focus on
139 .. note:: If you suspect your L2 (i.e. nested guest) is running slower,
191 On AMD systems, once an L1 guest has started an L2 guest, the L1 guest
193 "savevm"/"loadvm") until the L2 guest shuts down. Attempting to migrate
194 or save-and-load an L1 guest while an L2 guest is running will result in
199 actually running L2 guests, is expected to function normally even on AMD
202 Migrating an L2 guest is always expected to succeed, so all the following
[all …]
/linux-6.1.9/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-dt.txt33 next-level-cache = <&L2>;
47 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
59 next-level-cache = <&L2>;
/linux-6.1.9/Documentation/devicetree/bindings/arm/calxeda/
Dl2ecc.yaml7 title: Calxeda Highbank L2 cache ECC
10 Binding for the Calxeda Highbank L2 cache controller ECC device.
11 This does not cover the actual L2 cache controller control registers,
/linux-6.1.9/Documentation/devicetree/bindings/opp/
Dopp-v2.yaml35 next-level-cache = <&L2>;
46 next-level-cache = <&L2>;
92 next-level-cache = <&L2>;
103 next-level-cache = <&L2>;
114 next-level-cache = <&L2>;
125 next-level-cache = <&L2>;
176 next-level-cache = <&L2>;
187 next-level-cache = <&L2>;
198 next-level-cache = <&L2>;
209 next-level-cache = <&L2>;
/linux-6.1.9/drivers/net/ethernet/intel/iavf/
Diavf_common.c549 IAVF_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
550 IAVF_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
551 IAVF_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
554 IAVF_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
555 IAVF_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
558 IAVF_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
559 IAVF_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
560 IAVF_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
561 IAVF_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
562 IAVF_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
[all …]
/linux-6.1.9/Documentation/locking/
Dlockdep-design.rst22 dependency can be understood as lock order, where L1 -> L2 suggests that
23 a task is attempting to acquire L2 while holding L1. From lockdep's
24 perspective, the two locks (L1 and L2) are not necessarily related; that
145 <L1> -> <L2>
146 <L2> -> <L1>
521 L1 -> L2
523 , which means lockdep has seen L1 held before L2 held in the same context at runtime.
524 And in deadlock detection, we care whether we could get blocked on L2 with L1 held,
525 IOW, whether there is a locker L3 that L1 blocks L3 and L2 gets blocked by L3. So
526 we only care about 1) what L1 blocks and 2) what blocks L2. As a result, we can combine
[all …]
/linux-6.1.9/arch/powerpc/perf/
Disa207-common.c226 ret = PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT); in isa207_find_source()
260 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT); in isa207_find_source()
262 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM); in isa207_find_source()
269 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HIT) | P(HOPS, 0); in isa207_find_source()
271 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HITM) | P(HOPS, 0); in isa207_find_source()
/linux-6.1.9/Documentation/devicetree/bindings/memory-controllers/
Dbaikal,bt1-l2-ctl.yaml8 title: Baikal-T1 L2-cache Control Block
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
17 L2-cache controller block is responsible for the tuning. Its DT node is
/linux-6.1.9/arch/powerpc/boot/dts/fsl/
Dmpc8572ds_camp_core1.dts5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
58 cache-size = <0x80000>; // L2, 512K
80 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
/linux-6.1.9/Documentation/driver-api/
Dedac.rst145 - CPU caches (L1 and L2)
155 For example, a cache could be composed of L1, L2 and L3 levels of cache.
156 Each CPU core would have its own L1 cache, while sharing L2 and maybe L3
164 cpu/cpu0/.. <L1 and L2 block directory>
167 /L2-cache/ce_count
169 cpu/cpu1/.. <L1 and L2 block directory>
172 /L2-cache/ce_count
176 the L1 and L2 directories would be "edac_device_block's"
/linux-6.1.9/Documentation/networking/
Dipvlan.rst14 the master device share the L2 with its slave devices. I have developed this
45 (b) This command will create IPvlan link in L2 bridge mode::
49 (c) This command will create an IPvlan device in L2 private mode::
53 (d) This command will create an IPvlan device in L2 vepa mode::
61 IPvlan has two modes of operation - L2 and L3. For a given master device,
68 4.1 L2 mode:
81 master device for the L2 processing and routing from that instance will be
133 namespace where L2 on the slave could be changed / misused.
/linux-6.1.9/Documentation/admin-guide/perf/
Dqcom_l2_pmu.rst5 This driver supports the L2 cache clusters found in Qualcomm Technologies
6 Centriq SoCs. There are multiple physical L2 cache clusters, each with their
9 There is one logical L2 PMU exposed, which aggregates the results from
/linux-6.1.9/Documentation/devicetree/bindings/arm/cpu-enable-method/
Dnuvoton,npcm750-smp30 next-level-cache = <&L2>;
39 next-level-cache = <&L2>;

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