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/linux-6.1.9/Documentation/translations/zh_CN/core-api/irq/
Dirq-domain.rst16 目前Linux内核的设计使用了一个巨大的数字空间，每个独立的IRQ源都被分配了一个不
19 个中断控制器都能得到非重复的Linux IRQ号（数字）分配。
23 避免了重新实现与IRQ核心系统相同的回调机制。
25 在这里，中断号与硬件中断号离散了所有种类的对应关系：而在过去，IRQ号可以选择，
26 使它们与硬件IRQ线进入根中断控制器（即实际向CPU发射中断线的组件）相匹配，现
29 出于这个原因，我们需要一种机制将控制器本地中断号（即硬件irq编号）与Linux IRQ
33 提供任何对控制器本地IRQ(hwirq)号到Linux IRQ号空间的反向映射的支持。
35 irq_domain 库在 irq_alloc_desc*() API 的基础上增加了 hwirq 和 IRQ 号码
40 Device Tree和ACPI GSI），并且可以很容易地扩展以支持其它IRQ拓扑数据源。
50 在大多数情况下，irq_domain在开始时是空的，没有任何hwirq和IRQ号之间的映射。
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Dconcepts.rst12 什么是IRQ？
15 IRQ (Interrupt ReQuest) 指来自设备的中断请求。
17 多个设备可以连接到同一个引脚，从而共享一个IRQ。
19 IRQ编号是用来描述硬件中断源的内核标识符。通常它是一个到全局irq_desc数组的索引，
22 IRQ编号是对机器上可能的中断源的枚举。通常枚举的是系统中所有中断控制器的输入引脚
25 体系结构可以给IRQ号赋予额外的含义，在涉及到硬件手动配置的情况下，我们鼓励这样做。
26 ISA IRQ是赋予这种额外含义的一个典型例子。
Dirq-affinity.rst12 SMP IRQ 亲和性
20 /proc/irq/IRQ#/smp_affinity和/proc/irq/IRQ#/smp_affinity_list指定了哪些CPU能
21 够关联到一个给定的IRQ源，这两个文件包含了这些指定cpu的cpu位掩码(smp_affinity)和cpu列
22 表(smp_affinity_list)。它不允许关闭所有CPU， 同时如果IRQ控制器不支持中断请求亲和
23 (IRQ affinity)，那么所有cpu的默认值将保持不变(即关联到所有CPU).
25 /proc/irq/default_smp_affinity指明了适用于所有非激活IRQ的默认亲和性掩码。一旦IRQ被
50 现在让我们把这个IRQ限制在CPU(4-7)。
/linux-6.1.9/Documentation/translations/zh_CN/core-api/
Dgenericirq.rst18 Linux通用IRQ处理
32 本文档提供给那些希望在通用IRQ处理层的帮助下实现基于其架构的中断子系统的开发
58 这种高层IRQ处理程序的拆分实现使我们能够为每个特定的中断类型优化中断处理的流
61 最初的通用IRQ实现使用hw_interrupt_type结构体及其 ``->ack`` ``->end`` 等回
64 这两个IRQ类型共享许多低级的细节，但有不同的流处理。
68 分析一些架构的IRQ子系统的实现可以发现，他们中的大多数可以使用一套通用的“irq
69 流”方法，只需要添加芯片级的特定代码。这种分离对于那些需要IRQ流本身而不需要芯
70 片细节的特定（子）架构也很有价值——以提供了一个更透明的IRQ子系统设计。
77 的IRQ流实现“电平触发型”中断，并添加一个（子）架构特定的“边沿型”实现。
81 被使用，因为它能使IRQ子系统更小更干净。它已经被废弃三年了，即将被删除。
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/linux-6.1.9/Documentation/translations/zh_CN/PCI/
Dpci.rst58 - 注册IRQ处理程序(request_irq())
64 - 禁用设备产生的IRQ
65 - 释放IRQ（free_irq()）
186 - 注册IRQ处理程序（request_irq()）
201 - 分配一个IRQ（如果BIOS没有）。
284 注册IRQ处理函数
289 所有IRQ线的中断处理程序都应该用 ``IRQF_SHARED`` 注册，并使用devid将IRQ映射
290 到设备（记住，所有的PCI IRQ线都可以共享）。
293 中断号码代表从PCI设备到中断控制器的IRQ线。在MSI和MSI-X中（更多内容见下文），中
318 2) MSI避免了DMA/IRQ竞争条件。到主机内存的DMA被保证在MSI交付时对主机CPU是可
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/linux-6.1.9/Documentation/arm/
Dinterrupts.rst16 Secondly, the IRQ subsystem.
39 SA1111 IRQ handler, SA1111 IRQs can hold off SMC9196 IRQs indefinitely.
48 We also bring the idea of an IRQ "chip" (mainly to reduce the size of
57 * Acknowledge the IRQ.
58 * If this is a level-based IRQ, then it is expected to mask the IRQ
63 * Mask the IRQ in hardware.
67 * Unmask the IRQ in hardware.
71 * Re-run the IRQ
75 * Set the type of the IRQ.
90 the hardware IRQ if possible. If not, may call the handler
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/linux-6.1.9/Documentation/translations/zh_CN/driver-api/gpio/
Dlegacy.rst50 - 输入通常可作为 IRQ 信号,一般是沿触发,但有时是电平触发。这样的 IRQ
187 休眠，这不能在 IRQ 例程(中断上下文)中执行。
203 访问这样的 GPIO 需要一个允许休眠的上下文，例如线程 IRQ 处理例程，并用以上的
206 除了这些访问函数可能休眠，且它们操作的 GPIO 不能在硬件 IRQ 处理例程中访问的
352 GPIO 映射到 IRQ
355 GPIO 编号是无符号整数;IRQ 编号也是。这些构成了两个逻辑上不同的命名空间
356 (GPIO 0 不一定使用 IRQ 0)。你可以通过以下函数在它们之间实现映射::
358 /* 映射 GPIO 编号到 IRQ 编号 */
361 /* 映射 IRQ 编号到 GPIO 编号 (尽量避免使用) */
365 (例如,某些 GPIO 无法做为 IRQ 使用。)以下的编号错误是未经检测的:使用一个
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/linux-6.1.9/Documentation/translations/zh_TW/
DIRQ.txt26 何爲 IRQ?
28 一個 IRQ 是來自某個設備的一個中斷請求。目前，它們可以來自一個硬體引腳，
29 或來自一個數據包。多個設備可能連接到同個硬體引腳，從而共享一個 IRQ。
31 一個 IRQ 編號是用於告知硬體中斷源的內核標識。通常情況下，這是一個
35 一個 IRQ 編號是設備上某個可能的中斷源的枚舉。通常情況下，枚舉的編號是
39 架構可以對 IRQ 編號指定額外的含義，在硬體涉及任何手工配置的情況下，
40 是被提倡的。ISA 的 IRQ 是一個分配這類額外含義的典型例子。
Dgpio.txt61 - 輸入通常可作爲 IRQ 信號,一般是沿觸發,但有時是電平觸發。這樣的 IRQ
194 休眠，這不能在 IRQ 例程(中斷上下文)中執行。
210 訪問這樣的 GPIO 需要一個允許休眠的上下文，例如線程 IRQ 處理例程，並用以上的
213 除了這些訪問函數可能休眠，且它們操作的 GPIO 不能在硬體 IRQ 處理例程中訪問的
358 GPIO 映射到 IRQ
360 GPIO 編號是無符號整數;IRQ 編號也是。這些構成了兩個邏輯上不同的命名空間
361 (GPIO 0 不一定使用 IRQ 0)。你可以通過以下函數在它們之間實現映射:
363 /* 映射 GPIO 編號到 IRQ 編號 */
366 /* 映射 IRQ 編號到 GPIO 編號 (儘量避免使用) */
370 (例如,某些 GPIO 無法做爲 IRQ 使用。)以下的編號錯誤是未經檢測的:使用一個
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/linux-6.1.9/Documentation/core-api/irq/
Dirq-domain.rst6 space where each separate IRQ source is assigned a different number.
10 IRQ numbers.
15 mechanisms as the IRQ core system by modelling their interrupt
19 hardware interrupt numbers: whereas in the past, IRQ numbers could
20 be chosen so they matched the hardware IRQ line into the root
25 interrupt numbers, called hardware irq's, from Linux IRQ numbers.
29 the controller-local IRQ (hwirq) number into the Linux IRQ number
32 The irq_domain library adds mapping between hwirq and IRQ numbers on
39 be easily extended to support other IRQ topology data sources.
51 between hwirq and IRQ numbers. Mappings are added to the irq_domain
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Dconcepts.rst2 What is an IRQ?
5 An IRQ is an interrupt request from a device.
8 sharing an IRQ.
10 An IRQ number is a kernel identifier used to talk about a hardware
15 An IRQ number is an enumeration of the possible interrupt sources on a
21 Architectures can assign additional meaning to the IRQ numbers, and
Dirq-affinity.rst2 SMP IRQ affinity
10 /proc/irq/IRQ#/smp_affinity and /proc/irq/IRQ#/smp_affinity_list specify
11 which target CPUs are permitted for a given IRQ source. It's a bitmask
13 allowed to turn off all CPUs, and if an IRQ controller does not support
14 IRQ affinity then the value will not change from the default of all cpus.
17 to all non-active IRQs. Once IRQ is allocated/activated its affinity bitmask
43 Now lets restrict that IRQ to CPU(4-7).
/linux-6.1.9/Documentation/driver-api/hte/
Dtegra194-hte.rst10 (Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the
34 LIC (Legacy Interrupt Controller) IRQ GTE
37 This GTE instance timestamps LIC IRQ lines in real time. There are 352 IRQ
40 provides an example of how a consumer can request an IRQ line. Since it is a
41 one-to-one mapping with IRQ GTE provider, consumers can simply specify the IRQ
45 The provider source code of both IRQ and GPIO GTE instances is located at
47 ``drivers/hte/hte-tegra194-test.c`` demonstrates HTE API usage for both IRQ
/linux-6.1.9/Documentation/devicetree/bindings/interrupt-controller/
Darm,versatile-fpga-irq.txt3 One or more FPGA IRQ controllers can be synthesized in an ARM reference board
5 controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
12 as the FPGA IRQ controller has no configuration options for interrupt
34 - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
35 output is simply connected to the input of another IRQ controller,
36 then the parent IRQ shall be specified in this property.
Dcdns,xtensa-pic.txt8 When it's 1, the first cell is the internal IRQ number.
9 When it's 2, the first cell is the IRQ number, and the second cell
11 Periferals are usually connected to a fixed external IRQ, but for different
12 core variants it may be mapped to different internal IRQ.
13 IRQ sensitivity and priority are fixed for each core variant and may not be
/linux-6.1.9/Documentation/misc-devices/
Dpci-endpoint-test.rst16 #) raise legacy IRQ
17 #) raise MSI IRQ
18 #) raise MSI-X IRQ
34 Tests legacy IRQ
42 Changes driver IRQ type configuration. The IRQ type
45 Gets driver IRQ type configuration.
/linux-6.1.9/arch/sh/boards/mach-microdev/
Dirq.c42 # error Inconsistancy in defining the IRQ# for Keyboard!
46 # error Inconsistancy in defining the IRQ# for Ethernet!
50 # error Inconsistancy in defining the IRQ# for USB!
54 # error Inconsistancy in defining the IRQ# for PS/2 Mouse!
58 # error Inconsistancy in defining the IRQ# for secondary IDE!
62 # error Inconsistancy in defining the IRQ# for primary IDE!
/linux-6.1.9/Documentation/translations/zh_CN/loongarch/
Dirq-chip-model.rst9 LoongArch的IRQ芯片模型（层级关系）
13 中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（
20 断控制器（在配套芯片组里面）。这些中断控制器（或者说IRQ芯片）以一种层次树的组织形式
21 级联在一起，一共有两种层级关系模型（传统IRQ模型和扩展IRQ模型）。
23 传统IRQ模型
59 扩展IRQ模型
/linux-6.1.9/Documentation/ia64/
Dirq-redir.rst2 IRQ affinity on IA64 platforms
8 By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be
13 IRQ target is one particular CPU and cannot be a mask of several
29 Set the default route for IRQ number 41 to CPU 6 in lowest priority
36 cat /proc/irq/IRQ#/smp_affinity
48 If the platform features IRQ redirection (info provided by SAL) all
52 for the IRQ routing. Currently in Linux XTP registers can have three
59 The IRQ is routed to the CPU with lowest XTP register value, the
77 For systems like the NEC AzusA we get IRQ node-affinity for free. This
/linux-6.1.9/Documentation/devicetree/bindings/rtc/
Disil,isl12057.txt10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
15 be set when the IRQ#2 pin of the chip is not connected to the SoC but
26 the availability of an IRQ line connected to the SoC.
29 Example isl12057 node without IRQ#2 pin connected (no alarm support):
37 Example isl12057 node with IRQ#2 pin connected to main SoC via MPP6 (note
40 SoC, and the main function of the MPP used as IRQ line, i.e.
67 Example isl12057 node without IRQ#2 pin connected to the SoC but to a
/linux-6.1.9/Documentation/core-api/
Dgenericirq.rst4 Linux generic IRQ handling
23 generic IRQ handling layer.
51 This split implementation of high-level IRQ handlers allows us to
56 The original general IRQ implementation used hw_interrupt_type
61 ``ioapic_edge_irq`` IRQ-type which share many of the low-level details but
67 Analysing a couple of architecture's IRQ subsystem implementations
71 IRQ flow itself but not in the chip details - and thus provides a more
72 transparent IRQ subsystem design.
82 IRQ-flow implementation for 'level type' interrupts and add a
89 enables smaller and cleaner IRQ subsystems. It's deprecated for three
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/linux-6.1.9/Documentation/power/
Dsuspend-and-interrupts.rst43 The IRQF_NO_SUSPEND flag is used to indicate that to the IRQ subsystem when
45 leave the corresponding IRQ enabled so as to allow the interrupt to work as
50 Note that the IRQF_NO_SUSPEND flag affects the entire IRQ and not just one
51 user of it. Thus, if the IRQ is shared, all of the interrupt handlers installed
54 the IRQ's users. For this reason, using IRQF_NO_SUSPEND and IRQF_SHARED at the
75 The IRQ subsystem provides two helper functions to be used by device drivers for
77 handling the given IRQ as a system wakeup interrupt line and disable_irq_wake()
80 Calling enable_irq_wake() causes suspend_device_irqs() to treat the given IRQ
81 in a special way. Namely, the IRQ remains enabled, by on the first interrupt
105 IRQ subsystem to trigger a system wakeup.
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/linux-6.1.9/drivers/pinctrl/renesas/
Dpfc-r8a73a4.c238 #define IRQ(a) IRQ##a##_MARK macro
240 F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */ enumerator
241 F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1), enumerator
242 F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2), enumerator
243 F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3), enumerator
244 F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4), enumerator
245 F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5), enumerator
246 F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6), enumerator
247 F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7), enumerator
248 F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8), enumerator
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/linux-6.1.9/Documentation/tools/rtla/
Drtla-timerlat-hist.rst44 …Index IRQ-000 Thr-000 IRQ-001 Thr-001 IRQ-002 Thr-002 IRQ-003 Thr-003 IRQ-004 …
/linux-6.1.9/Documentation/virt/kvm/devices/
Dmpic.rst34 IRQ input line for each standard openpic source. 0 is inactive and 1
41 "attr" is the IRQ number. IRQ numbers for standard sources are the
44 IRQ Routing:
46 The MPIC emulation supports IRQ routing. Only a single MPIC device can
58 Access to non-SRC interrupts is not implemented through IRQ routing mechanisms.

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