Searched refs:IPI (Results 1 – 25 of 37) sorted by relevance
12
7 title: Xilinx IPI(Inter Processor Interrupt) mailbox controller10 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage11 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI15 | Xilinx ZynqMP IPI Controller |27 Hardware | | IPI Agent | | IPI Buffers | |32 | Xilinx IPI Agent Block |63 Remote Xilinx IPI agent ID of which the mailbox is connected to.78 Remote Xilinx IPI agent ID of which the mailbox is connected to.84 It contains tx(0) or rx(1) channel IPI id number.
49 order to perform some KVM maintenance. To do so, an IPI is sent, forcing55 1) Send an IPI. This forces a guest mode exit.70 as well as to avoid sending unnecessary IPIs (see "IPI Reduction"), and71 even to ensure IPI acknowledgements are waited upon (see "Waiting for160 then the caller will wait for each VCPU to acknowledge its IPI before162 If, for example, the VCPU is sleeping, so no IPI is necessary, then192 kick will send an IPI to force an exit from guest mode when necessary.197 enter guest mode. This means that an optimized implementation (see "IPI198 Reduction") must be certain when it's safe to not send the IPI. One208 !kvm_request_pending() on its last check and then not receiving an IPI for[all …]
26 在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，31 | IPI | --> | CPUINTC | <-- | Timer |62 在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，67 | IPI | --> | CPUINTC | <-- | Timer |
11 # when returning from IPI handler, and when returning to user-space.15 # x86-32 uses IRET as return from interrupt, which takes care of the IPI.19 # x86-64 uses IRET as return from interrupt, which takes care of the IPI.
25 IPI（以及处理IPI的相关成本）。
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go28 | IPI | --> | CPUINTC | <-- | Timer |59 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go65 | IPI | --> | CPUINTC | <-- | Timer |
112 Once a task has been selected for all the siblings in the core, an IPI is sent to113 siblings for whom a new task was selected. Siblings on receiving the IPI will130 When the highest priority task is selected to run, a reschedule-IPI is sent to142 (victim) to enter idle mode. This is because the sending of the IPI would bring145 which may not be worth protecting. It is also possible that the IPI is received171 IPI processing delays173 Core scheduling selects only trusted tasks to run together. IPI is used to notify175 receiving of the IPI on some arch (on x86, this has not been observed). This may177 IPI. Even though cache is flushed on entry to user mode, victim tasks on siblings
50 * Pending IPI (inter-processor interrupt) priority, 8 bits51 Zero is the highest priority, 255 means no IPI is pending.54 Zero means no interrupt pending, 2 means an IPI is pending
61 interrupt of the device being passed-through or the initial IPI ESB
71 non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC).127 2 = MPIC inter-processor interrupt (IPI)130 the MPIC IPI number. The type-specific193 * MPIC IPI interrupts. Note the interrupt
12 a remote vCPU to avoid sending an IPI (and the associated13 cost of handling the IPI) when performing a wakeup.
339 HAC, IPI, SPDIF, HUDI, I2C, enumerator365 INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),425 DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },430 { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
27 each of which results in an IPI to the target CPU.48 The dotted arrows denote indirect action, for example, an IPI55 ``smp_call_function_single()`` to send the CPU an IPI, which96 | IPI the CPU to safely interact with the upcoming |105 | IPI the CPU. |128 that the CPU went idle while the IPI was in flight. If the CPU is idle,142 grace periods. In addition, attempting to IPI offline CPUs will result143 in splats, but failing to IPI online CPUs can result in too-short grace231 For RCU-sched, there is an additional check: If the IPI has interrupted235 For RCU-preempt, there is no specific check for idle in the IPI handler[all …]
261 bool "Xilinx ZynqMP IPI Mailbox"264 Say yes here to add support for Xilinx IPI mailbox driver.266 between processors with Xilinx ZynqMP IPI. It will place the267 message to the IPI buffer and will access the IPI control
166 :Purpose: Hypercall used to yield if the IPI target vCPU is preempted170 :Usage example: When sending a call-function IPI-many to vCPUs, yield if171 any of the IPI target vCPUs was preempted.
51 VECTOR handle_interrupt ; (19) Inter core Interrupt (IPI)53 VECTOR handle_interrupt ; (21) Software Triggered Intr (Self IPI)
69 // Example with IPI mailbox method:
147 /* IPI called on each CPU. */
41 This use IPI and IPC to communicate with remote processors.
83 # Generic IRQ IPI support
70 enabling and disabling static keys invoke IPI broadcasts, the latency
57 1 Soft-irq. Uses IPI to complete IOs across CPU nodes. Simulates the overhead
153 /* IPI called on each CPU. */
288 unless absolutely necessary. Please consider using an IPI to wake up
160 global clock event devices. The support of such hardware would involve IPI