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Searched refs:IP0_31_28 (Results 1 – 9 of 9) sorted by relevance

/linux-6.1.9/drivers/pinctrl/renesas/
Dpfc-r8a77970.c59 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
170 #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0… macro
275 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
420 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
421 PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
422 PINMUX_IPSR_GPSR(IP0_31_28, A7),
423 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
2232 IP0_31_28
Dpfc-r8a77980.c60 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
203 #define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0)… macro
324 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
492 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
493 PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
494 PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
495 PINMUX_IPSR_GPSR(IP0_31_28, A7),
496 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
2685 IP0_31_28
Dpfc-r8a77995.c87 #define GPSR1_0 F_(DU_DB0, IP0_31_28)
216 #define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_… macro
366 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
559 PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
560 PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
561 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
2673 IP0_31_28
Dpfc-r8a77950.c142 #define GPSR2_1 F_(IRQ1, IP0_31_28)
260 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
442 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
674 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
675 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
676 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
677 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
678 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
679 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
4910 IP0_31_28
Dpfc-r8a77951.c143 #define GPSR2_1 F_(IRQ1, IP0_31_28)
261 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
452 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
681 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
682 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
683 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
684 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
685 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
686 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
687 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
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Dpfc-r8a7796.c148 #define GPSR2_1 F_(IRQ1, IP0_31_28)
266 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
457 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
686 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
687 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
688 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
689 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
690 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
691 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
692 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
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Dpfc-r8a77965.c148 #define GPSR2_1 F_(IRQ1, IP0_31_28)
266 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
457 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
687 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
688 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
689 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
690 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
691 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
692 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
693 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
[all …]
Dpfc-r8a77990.c129 #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28)
220 #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0)… macro
392 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
578 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1),
579 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
580 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1),
581 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0),
4787 IP0_31_28
Dpfc-r8a77470.c573 PINMUX_IPSR_GPSR(IP0_31_28, SD0_WP),
574 PINMUX_IPSR_GPSR(IP0_31_28, IRQ7),
575 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_TX_A, SEL_CAN0_0),