Searched refs:IOMEM (Results 1 – 25 of 49) sorted by relevance
12
58 #define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0)59 #define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1)60 #define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2)61 #define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3)62 #define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4)63 #define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5)66 #define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6)67 #define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7)70 #define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8)71 #define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9)[all …]
28 #define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */29 #define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */30 #define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */31 #define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */32 #define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */33 #define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */34 #define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
19 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)26 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)30 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)47 #define VA_SPEAR320_SOC_CONFIG_BASE IOMEM(0xFE000000)52 #define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)55 #define VA_SYSRAM0_BASE IOMEM(0xF9800000)59 #define VA_PERIP_GRP1_BASE IOMEM(0xFD000000)61 #define VA_UART_BASE IOMEM(0xFD000000)64 #define VA_MISC_BASE IOMEM(0xFD700000)67 #define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000)[all …]
24 #define PERIPH_VIRT IOMEM(0xf2000000)32 #define SMEMC_VIRT IOMEM(0xf6000000)39 #define DMEMC_VIRT IOMEM(0xf6100000)51 #define NAND_VIRT IOMEM(0xf6300000)58 #define IMEMC_VIRT IOMEM(0xfe000000)
72 #define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000)85 #define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000)86 #define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000)
68 #define ZEUS_CPLD IOMEM(0xf0000000)76 #define ZEUS_PC104IO IOMEM(0xf1000000)
32 #define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
13 #define LPD270_CPLD_VIRT IOMEM(0xf0000000)
20 #define TS72XX_MODEL_VIRT_BASE IOMEM(0xfebff000)32 #define TS72XX_OPTIONS_VIRT_BASE IOMEM(0xfebfe000)40 #define TS72XX_OPTIONS2_VIRT_BASE IOMEM(0xfebfd000)47 #define TS72XX_CPLDVER_VIRT_BASE IOMEM(0xfebfc000)
19 #define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x))26 #define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x))
34 #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */37 #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */40 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */43 #define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)46 #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)49 #define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
16 #define APB_VIRT_BASE IOMEM(0xfe000000)20 #define AXI_VIRT_BASE IOMEM(0xfe200000)24 #define PGU_VIRT_BASE IOMEM(0xfe400000)
98 #define IO_IRAM_VIRT IOMEM(0xFE400000)102 #define IO_CPU_VIRT IOMEM(0xFE440000)106 #define IO_PPSB_VIRT IOMEM(0xFE200000)110 #define IO_APB_VIRT IOMEM(0xFE000000)
23 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)36 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)40 #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfec00000)44 #define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe400000)
10 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x))) macro15 #define MT7621_SYSC_BASE IOMEM(0x1E000000)
36 IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )40 #define __MREG(x) IOMEM(io_p2v(x))
12 #define IOMEM(x) (x) macro
90 gic_init(IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), in cns3xxx_init_irq()91 IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT)); in cns3xxx_init_irq()96 u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT); in cns3xxx_power_off()251 cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT); in cns3xxx_timer_init()379 u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); in cns3xxx_init()
30 #define EASI_BASE IOMEM(0xe5000000)34 #define IO_BASE IOMEM(0xe0000000)
5 #define V7M_SCS_ICTR IOMEM(0xe000e004)8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
37 #define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000)53 #define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
181 #define UX500_VIRT_ROM IOMEM(0xf0000000)188 #define __io_address(n) IOMEM(IO_ADDRESS(n))
29 #define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
64 return readl(IOMEM(c->regs + section_offset + port_offset)); in zevio_gpio_port_get()71 writel(val, IOMEM(c->regs + section_offset + port_offset)); in zevio_gpio_port_set()