| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v1_0.c | 190 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
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| D | gfxhub_v2_0.c | 229 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v2_0_init_cache_regs()
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| D | gfxhub_v3_0_3.c | 233 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v3_0_3_init_cache_regs()
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| D | gfxhub_v3_0.c | 230 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v3_0_init_cache_regs()
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| D | mmhub_v3_0_2.c | 249 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v3_0_2_init_cache_regs()
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| D | mmhub_v3_0_1.c | 250 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v3_0_1_init_cache_regs()
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| D | mmhub_v2_0.c | 300 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v2_0_init_cache_regs()
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| D | mmhub_v2_3.c | 224 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v2_3_init_cache_regs()
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| D | mmhub_v3_0.c | 256 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v3_0_init_cache_regs()
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| D | mmhub_v1_0.c | 176 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
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| D | gfxhub_v2_1.c | 232 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v2_1_init_cache_regs()
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| D | gmc_v7_0.c | 646 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
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| D | mmhub_v1_7.c | 196 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v1_7_init_cache_regs()
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| D | sid.h | 381 #define INVALIDATE_L2_CACHE (1 << 1) macro
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| D | gmc_v8_0.c | 870 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
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| D | mmhub_v9_4.c | 229 INVALIDATE_L2_CACHE, 1); in mmhub_v9_4_init_cache_regs()
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| /linux-6.1.9/drivers/gpu/drm/radeon/ |
| D | rv770d.h | 649 #define INVALIDATE_L2_CACHE (1 << 1) macro
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| D | nid.h | 119 #define INVALIDATE_L2_CACHE (1 << 1) macro
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| D | sid.h | 380 #define INVALIDATE_L2_CACHE (1 << 1) macro
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| D | cikd.h | 498 #define INVALIDATE_L2_CACHE (1 << 1) macro
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| D | evergreend.h | 1157 #define INVALIDATE_L2_CACHE (1 << 1) macro
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| D | r600d.h | 594 #define INVALIDATE_L2_CACHE (1 << 1) macro
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| D | ni.c | 1287 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable()
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| D | si.c | 4306 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in si_pcie_gart_enable()
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| D | cik.c | 5445 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable()
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