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/linux-6.1.9/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
Dirq.c25 const irq_ID_t ID);
28 const irq_ID_t ID);
60 const irq_ID_t ID) in irq_clear_all() argument
64 assert(ID < N_IRQ_ID); in irq_clear_all()
65 assert(IRQ_N_CHANNEL[ID] <= HRT_DATA_WIDTH); in irq_clear_all()
67 if (IRQ_N_CHANNEL[ID] < HRT_DATA_WIDTH) { in irq_clear_all()
68 mask = ~((~(hrt_data)0) >> IRQ_N_CHANNEL[ID]); in irq_clear_all()
71 irq_reg_store(ID, in irq_clear_all()
80 const irq_ID_t ID, in irq_enable_channel() argument
83 unsigned int mask = irq_reg_load(ID, in irq_enable_channel()
[all …]
Dfifo_monitor.c44 const fifo_monitor_ID_t ID,
49 const fifo_monitor_ID_t ID,
54 const fifo_monitor_ID_t ID, in fifo_channel_get_state() argument
63 state->src_valid = fifo_monitor_status_valid(ID, in fifo_channel_get_state()
66 state->fifo_accept = fifo_monitor_status_accept(ID, in fifo_channel_get_state()
69 state->fifo_valid = fifo_monitor_status_valid(ID, in fifo_channel_get_state()
72 state->sink_accept = fifo_monitor_status_accept(ID, in fifo_channel_get_state()
77 state->src_valid = fifo_monitor_status_valid(ID, in fifo_channel_get_state()
80 state->fifo_accept = fifo_monitor_status_accept(ID, in fifo_channel_get_state()
83 state->fifo_valid = fifo_monitor_status_valid(ID, in fifo_channel_get_state()
[all …]
Dinput_formatter.c61 const input_formatter_ID_t ID) in input_formatter_rst() argument
66 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_rst()
68 addr = HIVE_IF_SRST_ADDRESS[ID]; in input_formatter_rst()
69 rst = HIVE_IF_SRST_MASK[ID]; in input_formatter_rst()
75 if (!HIVE_IF_BIN_COPY[ID]) { in input_formatter_rst()
76 input_formatter_reg_store(ID, addr, rst); in input_formatter_rst()
83 const input_formatter_ID_t ID) in input_formatter_get_alignment() argument
85 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_get_alignment()
87 return input_formatter_alignment[ID]; in input_formatter_get_alignment()
91 const input_formatter_ID_t ID, in input_formatter_set_fifo_blocking_mode() argument
[all …]
Dsp_private.h26 const sp_ID_t ID, in sp_ctrl_store() argument
30 assert(ID < N_SP_ID); in sp_ctrl_store()
31 assert(SP_CTRL_BASE[ID] != (hrt_address)-1); in sp_ctrl_store()
32 ia_css_device_store_uint32(SP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); in sp_ctrl_store()
37 const sp_ID_t ID, in sp_ctrl_load() argument
40 assert(ID < N_SP_ID); in sp_ctrl_load()
41 assert(SP_CTRL_BASE[ID] != (hrt_address)-1); in sp_ctrl_load()
42 return ia_css_device_load_uint32(SP_CTRL_BASE[ID] + reg * sizeof(hrt_data)); in sp_ctrl_load()
46 const sp_ID_t ID, in sp_ctrl_getbit() argument
50 hrt_data val = sp_ctrl_load(ID, reg); in sp_ctrl_getbit()
[all …]
Dgp_device.c24 const gp_device_ID_t ID, in gp_device_get_state() argument
27 assert(ID < N_GP_DEVICE_ID); in gp_device_get_state()
30 state->syncgen_enable = gp_device_reg_load(ID, in gp_device_get_state()
32 state->syncgen_free_running = gp_device_reg_load(ID, in gp_device_get_state()
34 state->syncgen_pause = gp_device_reg_load(ID, in gp_device_get_state()
36 state->nr_frames = gp_device_reg_load(ID, in gp_device_get_state()
38 state->syngen_nr_pix = gp_device_reg_load(ID, in gp_device_get_state()
40 state->syngen_nr_pix = gp_device_reg_load(ID, in gp_device_get_state()
42 state->syngen_nr_lines = gp_device_reg_load(ID, in gp_device_get_state()
44 state->syngen_hblank_cycles = gp_device_reg_load(ID, in gp_device_get_state()
[all …]
Disp_private.h31 const isp_ID_t ID, in isp_ctrl_store() argument
35 assert(ID < N_ISP_ID); in isp_ctrl_store()
36 assert(ISP_CTRL_BASE[ID] != (hrt_address) - 1); in isp_ctrl_store()
38 ia_css_device_store_uint32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); in isp_ctrl_store()
40 hrt_master_port_store_32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); in isp_ctrl_store()
46 const isp_ID_t ID, in isp_ctrl_load() argument
49 assert(ID < N_ISP_ID); in isp_ctrl_load()
50 assert(ISP_CTRL_BASE[ID] != (hrt_address) - 1); in isp_ctrl_load()
52 return ia_css_device_load_uint32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data)); in isp_ctrl_load()
54 return hrt_master_port_uload_32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data)); in isp_ctrl_load()
[all …]
Disp.c28 const isp_ID_t ID, in cnd_isp_irq_enable() argument
32 isp_ctrl_setbit(ID, ISP_IRQ_READY_REG, ISP_IRQ_READY_BIT); in cnd_isp_irq_enable()
34 isp_ctrl_setbit(ID, ISP_IRQ_CLEAR_REG, ISP_IRQ_CLEAR_BIT); in cnd_isp_irq_enable()
36 isp_ctrl_clearbit(ID, ISP_IRQ_READY_REG, in cnd_isp_irq_enable()
43 const isp_ID_t ID, in isp_get_state() argument
47 hrt_data sc = isp_ctrl_load(ID, ISP_SC_REG); in isp_get_state()
58 state->pc = isp_ctrl_load(ID, ISP_PC_REG); in isp_get_state()
60 state->is_broken = isp_ctrl_getbit(ID, ISP_SC_REG, ISP_BROKEN_BIT); in isp_get_state()
61 state->is_idle = isp_ctrl_getbit(ID, ISP_SC_REG, ISP_IDLE_BIT); in isp_get_state()
62 state->is_sleeping = isp_ctrl_getbit(ID, ISP_SC_REG, ISP_SLEEPING_BIT); in isp_get_state()
[all …]
Dinput_system.c45 static void receiver_rst(const rx_ID_t ID);
46 static void input_system_network_rst(const input_system_ID_t ID);
49 const input_system_ID_t ID,
54 const input_system_ID_t ID,
59 const input_system_ID_t ID,
64 const input_system_ID_t ID,
84 const input_system_ID_t ID,
89 const input_system_ID_t ID,
94 const input_system_ID_t ID,
99 const rx_ID_t ID,
[all …]
Ddma.c26 void dma_get_state(const dma_ID_t ID, dma_state_t *state) in dma_get_state() argument
31 assert(ID < N_DMA_ID); in dma_get_state()
34 tmp = dma_reg_load(ID, DMA_COMMAND_FSM_REG_IDX); in dma_get_state()
75 state->current_command = dma_reg_load(ID, in dma_get_state()
77 state->current_addr_a = dma_reg_load(ID, in dma_get_state()
79 state->current_addr_b = dma_reg_load(ID, in dma_get_state()
82 tmp = dma_reg_load(ID, in dma_get_state()
102 state->fsm_ctrl_source_dev = dma_reg_load(ID, in dma_get_state()
106 state->fsm_ctrl_source_addr = dma_reg_load(ID, in dma_get_state()
110 state->fsm_ctrl_source_stride = dma_reg_load(ID, in dma_get_state()
[all …]
Devent_fifo_private.h27 STORAGE_CLASS_EVENT_C void event_wait_for(const event_ID_t ID) in event_wait_for() argument
29 assert(ID < N_EVENT_ID); in event_wait_for()
30 assert(event_source_addr[ID] != ((hrt_address) - 1)); in event_wait_for()
31 (void)ia_css_device_load_uint32(event_source_addr[ID]); in event_wait_for()
35 STORAGE_CLASS_EVENT_C void cnd_event_wait_for(const event_ID_t ID, in cnd_event_wait_for() argument
39 event_wait_for(ID); in cnd_event_wait_for()
43 STORAGE_CLASS_EVENT_C hrt_data event_receive_token(const event_ID_t ID) in event_receive_token() argument
45 assert(ID < N_EVENT_ID); in event_receive_token()
46 assert(event_source_addr[ID] != ((hrt_address) - 1)); in event_receive_token()
47 return ia_css_device_load_uint32(event_source_addr[ID]); in event_receive_token()
[all …]
Dsp.c25 const sp_ID_t ID, in cnd_sp_irq_enable() argument
29 sp_ctrl_setbit(ID, SP_IRQ_READY_REG, SP_IRQ_READY_BIT); in cnd_sp_irq_enable()
31 sp_ctrl_setbit(ID, SP_IRQ_CLEAR_REG, SP_IRQ_CLEAR_BIT); in cnd_sp_irq_enable()
33 sp_ctrl_clearbit(ID, SP_IRQ_READY_REG, SP_IRQ_READY_BIT); in cnd_sp_irq_enable()
38 const sp_ID_t ID, in sp_get_state() argument
42 hrt_data sc = sp_ctrl_load(ID, SP_SC_REG); in sp_get_state()
47 state->pc = sp_ctrl_load(ID, SP_PC_REG); in sp_get_state()
54 !sp_ctrl_getbit(ID, SP_FIFO0_SINK_REG, SP_FIFO0_SINK_BIT); in sp_get_state()
56 !sp_ctrl_getbit(ID, SP_FIFO1_SINK_REG, SP_FIFO1_SINK_BIT); in sp_get_state()
58 !sp_ctrl_getbit(ID, SP_FIFO2_SINK_REG, SP_FIFO2_SINK_BIT); in sp_get_state()
[all …]
Dfifo_monitor_private.h33 const fifo_monitor_ID_t ID, in fifo_switch_set() argument
37 assert(ID == FIFO_MONITOR0_ID); in fifo_switch_set()
38 assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1); in fifo_switch_set()
40 (void)ID; in fifo_switch_set()
48 const fifo_monitor_ID_t ID, in fifo_switch_get() argument
51 assert(ID == FIFO_MONITOR0_ID); in fifo_switch_get()
52 assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1); in fifo_switch_get()
54 (void)ID; in fifo_switch_get()
60 const fifo_monitor_ID_t ID, in fifo_monitor_reg_store() argument
64 assert(ID < N_FIFO_MONITOR_ID); in fifo_monitor_reg_store()
[all …]
/linux-6.1.9/drivers/staging/media/atomisp/pci/css_2401_system/host/
Dpixelgen_private.h33 const pixelgen_ID_t ID, in pixelgen_ctrl_reg_load() argument
36 assert(ID < N_PIXELGEN_ID); in pixelgen_ctrl_reg_load()
37 assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address) - 1); in pixelgen_ctrl_reg_load()
38 return ia_css_device_load_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof( in pixelgen_ctrl_reg_load()
47 const pixelgen_ID_t ID, in pixelgen_ctrl_reg_store() argument
51 assert(ID < N_PIXELGEN_ID); in pixelgen_ctrl_reg_store()
52 assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1); in pixelgen_ctrl_reg_store()
54 ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof(hrt_data), in pixelgen_ctrl_reg_store()
70 const pixelgen_ID_t ID, in pixelgen_ctrl_get_state() argument
74 pixelgen_ctrl_reg_load(ID, _PXG_COM_ENABLE_REG_IDX); in pixelgen_ctrl_get_state()
[all …]
Dcsi_rx_private.h38 const csi_rx_frontend_ID_t ID, in csi_rx_fe_ctrl_reg_load() argument
41 assert(ID < N_CSI_RX_FRONTEND_ID); in csi_rx_fe_ctrl_reg_load()
42 assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); in csi_rx_fe_ctrl_reg_load()
43 return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof( in csi_rx_fe_ctrl_reg_load()
52 const csi_rx_frontend_ID_t ID, in csi_rx_fe_ctrl_reg_store() argument
56 assert(ID < N_CSI_RX_FRONTEND_ID); in csi_rx_fe_ctrl_reg_store()
57 assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); in csi_rx_fe_ctrl_reg_store()
59 ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(hrt_data), in csi_rx_fe_ctrl_reg_store()
68 const csi_rx_backend_ID_t ID, in csi_rx_be_ctrl_reg_load() argument
71 assert(ID < N_CSI_RX_BACKEND_ID); in csi_rx_be_ctrl_reg_load()
[all …]
Disys_stream2mmio_private.h44 const stream2mmio_ID_t ID, in stream2mmio_get_state() argument
53 for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) { in stream2mmio_get_state()
54 stream2mmio_get_sid_state(ID, i, &state->sid_state[i]); in stream2mmio_get_state()
63 const stream2mmio_ID_t ID, in stream2mmio_get_sid_state() argument
68 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_ACKNOWLEDGE_REG_ID); in stream2mmio_get_sid_state()
71 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_PIX_WIDTH_ID_REG_ID); in stream2mmio_get_sid_state()
74 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_START_ADDR_REG_ID); in stream2mmio_get_sid_state()
77 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_END_ADDR_REG_ID); in stream2mmio_get_sid_state()
80 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_STRIDE_REG_ID); in stream2mmio_get_sid_state()
83 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_NUM_ITEMS_REG_ID); in stream2mmio_get_sid_state()
[all …]
/linux-6.1.9/drivers/staging/media/atomisp/pci/
Disp2401_input_system_private.h27 static inline hrt_data ibuf_ctrl_reg_load(const ibuf_ctrl_ID_t ID, in ibuf_ctrl_reg_load() argument
30 assert(ID < N_IBUF_CTRL_ID); in ibuf_ctrl_reg_load()
31 assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); in ibuf_ctrl_reg_load()
32 return ia_css_device_load_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data)); in ibuf_ctrl_reg_load()
36 static inline void ibuf_ctrl_reg_store(const ibuf_ctrl_ID_t ID, in ibuf_ctrl_reg_store() argument
40 assert(ID < N_IBUF_CTRL_ID); in ibuf_ctrl_reg_store()
41 assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); in ibuf_ctrl_reg_store()
43 ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); in ibuf_ctrl_reg_store()
47 static inline void ibuf_ctrl_get_proc_state(const ibuf_ctrl_ID_t ID, in ibuf_ctrl_get_proc_state() argument
57 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_ITEMS_PER_STORE); in ibuf_ctrl_get_proc_state()
[all …]
Disp2400_input_system_private.h26 const input_system_ID_t ID, in input_system_reg_store() argument
30 assert(ID < N_INPUT_SYSTEM_ID); in input_system_reg_store()
31 assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); in input_system_reg_store()
32 ia_css_device_store_uint32(INPUT_SYSTEM_BASE[ID] + reg * sizeof(hrt_data), in input_system_reg_store()
38 const input_system_ID_t ID, in input_system_reg_load() argument
41 assert(ID < N_INPUT_SYSTEM_ID); in input_system_reg_load()
42 assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); in input_system_reg_load()
43 return ia_css_device_load_uint32(INPUT_SYSTEM_BASE[ID] + reg * sizeof( in input_system_reg_load()
48 const rx_ID_t ID, in receiver_reg_store() argument
52 assert(ID < N_RX_ID); in receiver_reg_store()
[all …]
/linux-6.1.9/drivers/scsi/aic7xxx/
Daic7xxx_osm_pci.c47 #define ID(x) ID_C(x, PCI_CLASS_STORAGE_SCSI) macro
51 ID(ID_AHA_2902_04_10_15_20C_30C),
53 ID(ID_AHA_2930CU),
54 ID(ID_AHA_1480A & ID_DEV_VENDOR_MASK),
55 ID(ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK),
56 ID(ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK),
57 ID(ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK),
59 ID(ID_AHA_2940),
60 ID(ID_AHA_3940),
61 ID(ID_AHA_398X),
[all …]
Daiclib.h163 ID(x), \
164 ID((x) | 0x0001000000000000ull), \
165 ID((x) | 0x0002000000000000ull), \
166 ID((x) | 0x0003000000000000ull), \
167 ID((x) | 0x0004000000000000ull), \
168 ID((x) | 0x0005000000000000ull), \
169 ID((x) | 0x0006000000000000ull), \
170 ID((x) | 0x0007000000000000ull), \
171 ID((x) | 0x0008000000000000ull), \
172 ID((x) | 0x0009000000000000ull), \
[all …]
/linux-6.1.9/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/
Disp_public.h30 const isp_ID_t ID,
42 const isp_ID_t ID,
55 const isp_ID_t ID,
68 const isp_ID_t ID,
80 const isp_ID_t ID,
93 const isp_ID_t ID,
106 const isp_ID_t ID,
120 const isp_ID_t ID,
135 const isp_ID_t ID,
150 const isp_ID_t ID,
[all …]
Dsp_public.h33 const sp_ID_t ID,
45 const sp_ID_t ID,
58 const sp_ID_t ID,
71 const sp_ID_t ID,
83 const sp_ID_t ID,
96 const sp_ID_t ID,
109 const sp_ID_t ID,
123 const sp_ID_t ID,
138 const sp_ID_t ID,
153 const sp_ID_t ID,
[all …]
Dmmu_public.h31 const mmu_ID_t ID,
42 const mmu_ID_t ID);
51 const mmu_ID_t ID);
68 const mmu_ID_t ID, in mmu_reg_store() argument
72 assert(ID < N_MMU_ID); in mmu_reg_store()
73 assert(MMU_BASE[ID] != (hrt_address) - 1); in mmu_reg_store()
74 ia_css_device_store_uint32(MMU_BASE[ID] + reg * sizeof(hrt_data), value); in mmu_reg_store()
87 const mmu_ID_t ID, in mmu_reg_load() argument
90 assert(ID < N_MMU_ID); in mmu_reg_load()
91 assert(MMU_BASE[ID] != (hrt_address) - 1); in mmu_reg_load()
[all …]
/linux-6.1.9/Documentation/translations/zh_CN/core-api/
Didr.rst18 ID分配
27 符、进程ID、网络协议中的数据包标识符、SCSI标记和设备实例编号。IDR和IDA为这个问题
28 提供了一个合理的解决方案，以避免每个人都自创。IDR提供将ID映射到指针的能力，而IDA
29 仅提供ID分配，因此内存效率更高。
39 您可以调用idr_alloc()来分配一个未使用的ID。通过调用idr_find()查询与该ID相关的指针，
40 并通过调用idr_remove()释放该ID。
42 如果需要更改与一个ID相关联的指针，可以调用idr_replace()。这样做的一个常见原因是通
43 过将 ``NULL`` 指针传递给分配函数来保留ID；用保留的ID初始化对象，最后将初始化的对
46 一些用户需要分配大于 ``INT_MAX`` 的ID。到目前为止，所有这些用户都满足 ``UINT_MAX``
47 的限制，他们使用idr_alloc_u32()。如果您需要超出u32的ID，我们将与您合作以满足您的
[all …]
/linux-6.1.9/drivers/pinctrl/cirrus/
Dpinctrl-lochnagar.c50 #define LN_PIN_GPIO(REV, ID, NAME, REG, SHIFT, INVERT) \ argument
51 static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = { \
56 #define LN_PIN_SAIF(REV, ID, NAME) \ argument
57 static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = \
60 #define LN_PIN_AIF(REV, ID) \ argument
61 LN_PIN_SAIF(REV, ID##_BCLK, LN_##ID##_STR"-bclk"); \
62 LN_PIN_SAIF(REV, ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
63 LN_PIN_SAIF(REV, ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
64 LN_PIN_SAIF(REV, ID##_TXDAT, LN_##ID##_STR"-txdat")
66 #define LN1_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \ argument
[all …]
/linux-6.1.9/drivers/char/agp/
Dvia-agp.c508 #define ID(x) \ macro
517 ID(PCI_DEVICE_ID_VIA_82C597_0),
518 ID(PCI_DEVICE_ID_VIA_82C598_0),
519 ID(PCI_DEVICE_ID_VIA_8501_0),
520 ID(PCI_DEVICE_ID_VIA_8601_0),
521 ID(PCI_DEVICE_ID_VIA_82C691_0),
522 ID(PCI_DEVICE_ID_VIA_8371_0),
523 ID(PCI_DEVICE_ID_VIA_8633_0),
524 ID(PCI_DEVICE_ID_VIA_XN266),
525 ID(PCI_DEVICE_ID_VIA_8361),
[all …]

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