Searched refs:ICL_PORT_DPLL_DEFAULT (Results 1 – 3 of 3) sorted by relevance
179 ICL_PORT_DPLL_DEFAULT, enumerator
3173 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; in icl_update_active_dpll()3202 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_combo_phy_dpll()3218 icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); in icl_compute_combo_phy_dpll()3234 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_combo_phy_dpll()3292 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_tc_phy_dplls()3296 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_tc_phy_dplls()3325 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()3329 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()3357 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()3408 for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) { in icl_put_dplls()
3461 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; in intel_ddi_get_clock()3528 port_dpll_id = ICL_PORT_DPLL_DEFAULT; in icl_ddi_tc_get_clock()