1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
24 *
25 */
26
27 #include <linux/gpio/consumer.h>
28 #include <linux/gpio/machine.h>
29 #include <linux/mfd/intel_soc_pmic.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/pinctrl/machine.h>
32 #include <linux/slab.h>
33 #include <linux/string_helpers.h>
34
35 #include <asm/unaligned.h>
36
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_edid.h>
39
40 #include <video/mipi_display.h>
41
42 #include "i915_drv.h"
43 #include "i915_reg.h"
44 #include "intel_de.h"
45 #include "intel_display_types.h"
46 #include "intel_dsi.h"
47 #include "intel_dsi_vbt.h"
48 #include "intel_gmbus_regs.h"
49 #include "vlv_dsi.h"
50 #include "vlv_dsi_regs.h"
51 #include "vlv_sideband.h"
52
53 #define MIPI_TRANSFER_MODE_SHIFT 0
54 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
55 #define MIPI_PORT_SHIFT 3
56
57 /* base offsets for gpio pads */
58 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
59 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
60 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
61 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
62 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
63 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
64 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
65 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
66 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
67 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100
68 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0
69 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0
70
71 #define VLV_GPIO_PCONF0(base_offset) (base_offset)
72 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8)
73
74 struct gpio_map {
75 u16 base_offset;
76 bool init;
77 };
78
79 static struct gpio_map vlv_gpio_table[] = {
80 { VLV_GPIO_NC_0_HV_DDI0_HPD },
81 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
82 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
83 { VLV_GPIO_NC_3_PANEL0_VDDEN },
84 { VLV_GPIO_NC_4_PANEL0_BKLTEN },
85 { VLV_GPIO_NC_5_PANEL0_BKLTCTL },
86 { VLV_GPIO_NC_6_HV_DDI1_HPD },
87 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
88 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
89 { VLV_GPIO_NC_9_PANEL1_VDDEN },
90 { VLV_GPIO_NC_10_PANEL1_BKLTEN },
91 { VLV_GPIO_NC_11_PANEL1_BKLTCTL },
92 };
93
94 struct i2c_adapter_lookup {
95 u16 slave_addr;
96 struct intel_dsi *intel_dsi;
97 acpi_handle dev_handle;
98 };
99
100 #define CHV_GPIO_IDX_START_N 0
101 #define CHV_GPIO_IDX_START_E 73
102 #define CHV_GPIO_IDX_START_SW 100
103 #define CHV_GPIO_IDX_START_SE 198
104
105 #define CHV_VBT_MAX_PINS_PER_FMLY 15
106
107 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8)
108 #define CHV_GPIO_GPIOEN (1 << 15)
109 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8)
110 #define CHV_GPIO_GPIOCFG_GPO (1 << 8)
111 #define CHV_GPIO_GPIOCFG_GPI (2 << 8)
112 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8)
113 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1)
114
115 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4)
116 #define CHV_GPIO_CFGLOCK (1 << 31)
117
118 /* ICL DSI Display GPIO Pins */
119 #define ICL_GPIO_DDSP_HPD_A 0
120 #define ICL_GPIO_L_VDDEN_1 1
121 #define ICL_GPIO_L_BKLTEN_1 2
122 #define ICL_GPIO_DDPA_CTRLCLK_1 3
123 #define ICL_GPIO_DDPA_CTRLDATA_1 4
124 #define ICL_GPIO_DDSP_HPD_B 5
125 #define ICL_GPIO_L_VDDEN_2 6
126 #define ICL_GPIO_L_BKLTEN_2 7
127 #define ICL_GPIO_DDPA_CTRLCLK_2 8
128 #define ICL_GPIO_DDPA_CTRLDATA_2 9
129
intel_dsi_seq_port_to_port(struct intel_dsi * intel_dsi,u8 seq_port)130 static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi,
131 u8 seq_port)
132 {
133 /*
134 * If single link DSI is being used on any port, the VBT sequence block
135 * send packet apparently always has 0 for the port. Just use the port
136 * we have configured, and ignore the sequence block port.
137 */
138 if (hweight8(intel_dsi->ports) == 1)
139 return ffs(intel_dsi->ports) - 1;
140
141 if (seq_port) {
142 if (intel_dsi->ports & BIT(PORT_B))
143 return PORT_B;
144 else if (intel_dsi->ports & BIT(PORT_C))
145 return PORT_C;
146 }
147
148 return PORT_A;
149 }
150
mipi_exec_send_packet(struct intel_dsi * intel_dsi,const u8 * data)151 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
152 const u8 *data)
153 {
154 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
155 struct mipi_dsi_device *dsi_device;
156 u8 type, flags, seq_port;
157 u16 len;
158 enum port port;
159
160 drm_dbg_kms(&dev_priv->drm, "\n");
161
162 flags = *data++;
163 type = *data++;
164
165 len = *((u16 *) data);
166 data += 2;
167
168 seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
169
170 port = intel_dsi_seq_port_to_port(intel_dsi, seq_port);
171
172 if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port]))
173 goto out;
174
175 dsi_device = intel_dsi->dsi_hosts[port]->device;
176 if (!dsi_device) {
177 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n",
178 port_name(port));
179 goto out;
180 }
181
182 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
183 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
184 else
185 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
186
187 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
188
189 switch (type) {
190 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
191 mipi_dsi_generic_write(dsi_device, NULL, 0);
192 break;
193 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
194 mipi_dsi_generic_write(dsi_device, data, 1);
195 break;
196 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
197 mipi_dsi_generic_write(dsi_device, data, 2);
198 break;
199 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
200 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
201 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
202 drm_dbg(&dev_priv->drm,
203 "Generic Read not yet implemented or used\n");
204 break;
205 case MIPI_DSI_GENERIC_LONG_WRITE:
206 mipi_dsi_generic_write(dsi_device, data, len);
207 break;
208 case MIPI_DSI_DCS_SHORT_WRITE:
209 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
210 break;
211 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
212 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
213 break;
214 case MIPI_DSI_DCS_READ:
215 drm_dbg(&dev_priv->drm,
216 "DCS Read not yet implemented or used\n");
217 break;
218 case MIPI_DSI_DCS_LONG_WRITE:
219 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
220 break;
221 }
222
223 if (DISPLAY_VER(dev_priv) < 11)
224 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
225
226 out:
227 data += len;
228
229 return data;
230 }
231
mipi_exec_delay(struct intel_dsi * intel_dsi,const u8 * data)232 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
233 {
234 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
235 u32 delay = *((const u32 *) data);
236
237 drm_dbg_kms(&i915->drm, "\n");
238
239 usleep_range(delay, delay + 10);
240 data += 4;
241
242 return data;
243 }
244
vlv_exec_gpio(struct intel_connector * connector,u8 gpio_source,u8 gpio_index,bool value)245 static void vlv_exec_gpio(struct intel_connector *connector,
246 u8 gpio_source, u8 gpio_index, bool value)
247 {
248 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
249 struct gpio_map *map;
250 u16 pconf0, padval;
251 u32 tmp;
252 u8 port;
253
254 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
255 drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n",
256 gpio_index);
257 return;
258 }
259
260 map = &vlv_gpio_table[gpio_index];
261
262 if (connector->panel.vbt.dsi.seq_version >= 3) {
263 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
264 port = IOSF_PORT_GPIO_NC;
265 } else {
266 if (gpio_source == 0) {
267 port = IOSF_PORT_GPIO_NC;
268 } else if (gpio_source == 1) {
269 drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n");
270 return;
271 } else {
272 drm_dbg_kms(&dev_priv->drm,
273 "unknown gpio source %u\n", gpio_source);
274 return;
275 }
276 }
277
278 pconf0 = VLV_GPIO_PCONF0(map->base_offset);
279 padval = VLV_GPIO_PAD_VAL(map->base_offset);
280
281 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
282 if (!map->init) {
283 /* FIXME: remove constant below */
284 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
285 map->init = true;
286 }
287
288 tmp = 0x4 | value;
289 vlv_iosf_sb_write(dev_priv, port, padval, tmp);
290 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
291 }
292
chv_exec_gpio(struct intel_connector * connector,u8 gpio_source,u8 gpio_index,bool value)293 static void chv_exec_gpio(struct intel_connector *connector,
294 u8 gpio_source, u8 gpio_index, bool value)
295 {
296 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
297 u16 cfg0, cfg1;
298 u16 family_num;
299 u8 port;
300
301 if (connector->panel.vbt.dsi.seq_version >= 3) {
302 if (gpio_index >= CHV_GPIO_IDX_START_SE) {
303 /* XXX: it's unclear whether 255->57 is part of SE. */
304 gpio_index -= CHV_GPIO_IDX_START_SE;
305 port = CHV_IOSF_PORT_GPIO_SE;
306 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
307 gpio_index -= CHV_GPIO_IDX_START_SW;
308 port = CHV_IOSF_PORT_GPIO_SW;
309 } else if (gpio_index >= CHV_GPIO_IDX_START_E) {
310 gpio_index -= CHV_GPIO_IDX_START_E;
311 port = CHV_IOSF_PORT_GPIO_E;
312 } else {
313 port = CHV_IOSF_PORT_GPIO_N;
314 }
315 } else {
316 /* XXX: The spec is unclear about CHV GPIO on seq v2 */
317 if (gpio_source != 0) {
318 drm_dbg_kms(&dev_priv->drm,
319 "unknown gpio source %u\n", gpio_source);
320 return;
321 }
322
323 if (gpio_index >= CHV_GPIO_IDX_START_E) {
324 drm_dbg_kms(&dev_priv->drm,
325 "invalid gpio index %u for GPIO N\n",
326 gpio_index);
327 return;
328 }
329
330 port = CHV_IOSF_PORT_GPIO_N;
331 }
332
333 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
334 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
335
336 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
337 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
338
339 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
340 vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
341 vlv_iosf_sb_write(dev_priv, port, cfg0,
342 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
343 CHV_GPIO_GPIOTXSTATE(value));
344 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
345 }
346
bxt_exec_gpio(struct intel_connector * connector,u8 gpio_source,u8 gpio_index,bool value)347 static void bxt_exec_gpio(struct intel_connector *connector,
348 u8 gpio_source, u8 gpio_index, bool value)
349 {
350 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
351 /* XXX: this table is a quick ugly hack. */
352 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
353 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
354
355 if (!gpio_desc) {
356 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
357 NULL, gpio_index,
358 value ? GPIOD_OUT_LOW :
359 GPIOD_OUT_HIGH);
360
361 if (IS_ERR_OR_NULL(gpio_desc)) {
362 drm_err(&dev_priv->drm,
363 "GPIO index %u request failed (%ld)\n",
364 gpio_index, PTR_ERR(gpio_desc));
365 return;
366 }
367
368 bxt_gpio_table[gpio_index] = gpio_desc;
369 }
370
371 gpiod_set_value(gpio_desc, value);
372 }
373
icl_exec_gpio(struct intel_connector * connector,u8 gpio_source,u8 gpio_index,bool value)374 static void icl_exec_gpio(struct intel_connector *connector,
375 u8 gpio_source, u8 gpio_index, bool value)
376 {
377 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
378
379 drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
380 }
381
382 enum {
383 MIPI_RESET_1 = 0,
384 MIPI_AVDD_EN_1,
385 MIPI_BKLT_EN_1,
386 MIPI_AVEE_EN_1,
387 MIPI_VIO_EN_1,
388 MIPI_RESET_2,
389 MIPI_AVDD_EN_2,
390 MIPI_BKLT_EN_2,
391 MIPI_AVEE_EN_2,
392 MIPI_VIO_EN_2,
393 };
394
icl_native_gpio_set_value(struct drm_i915_private * dev_priv,int gpio,bool value)395 static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
396 int gpio, bool value)
397 {
398 int index;
399
400 if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 11 && gpio >= MIPI_RESET_2))
401 return;
402
403 switch (gpio) {
404 case MIPI_RESET_1:
405 case MIPI_RESET_2:
406 index = gpio == MIPI_RESET_1 ? HPD_PORT_A : HPD_PORT_B;
407
408 /*
409 * Disable HPD to set the pin to output, and set output
410 * value. The HPD pin should not be enabled for DSI anyway,
411 * assuming the board design and VBT are sane, and the pin isn't
412 * used by a non-DSI encoder.
413 *
414 * The locking protects against concurrent SHOTPLUG_CTL_DDI
415 * modifications in irq setup and handling.
416 */
417 spin_lock_irq(&dev_priv->irq_lock);
418 intel_de_rmw(dev_priv, SHOTPLUG_CTL_DDI,
419 SHOTPLUG_CTL_DDI_HPD_ENABLE(index) |
420 SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index),
421 value ? SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index) : 0);
422 spin_unlock_irq(&dev_priv->irq_lock);
423 break;
424 case MIPI_AVDD_EN_1:
425 case MIPI_AVDD_EN_2:
426 index = gpio == MIPI_AVDD_EN_1 ? 0 : 1;
427
428 intel_de_rmw(dev_priv, PP_CONTROL(index), PANEL_POWER_ON,
429 value ? PANEL_POWER_ON : 0);
430 break;
431 case MIPI_BKLT_EN_1:
432 case MIPI_BKLT_EN_2:
433 index = gpio == MIPI_BKLT_EN_1 ? 0 : 1;
434
435 intel_de_rmw(dev_priv, PP_CONTROL(index), EDP_BLC_ENABLE,
436 value ? EDP_BLC_ENABLE : 0);
437 break;
438 case MIPI_AVEE_EN_1:
439 case MIPI_AVEE_EN_2:
440 index = gpio == MIPI_AVEE_EN_1 ? 1 : 2;
441
442 intel_de_rmw(dev_priv, GPIO(dev_priv, index),
443 GPIO_CLOCK_VAL_OUT,
444 GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT |
445 GPIO_CLOCK_VAL_MASK | (value ? GPIO_CLOCK_VAL_OUT : 0));
446 break;
447 case MIPI_VIO_EN_1:
448 case MIPI_VIO_EN_2:
449 index = gpio == MIPI_VIO_EN_1 ? 1 : 2;
450
451 intel_de_rmw(dev_priv, GPIO(dev_priv, index),
452 GPIO_DATA_VAL_OUT,
453 GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT |
454 GPIO_DATA_VAL_MASK | (value ? GPIO_DATA_VAL_OUT : 0));
455 break;
456 default:
457 MISSING_CASE(gpio);
458 }
459 }
460
mipi_exec_gpio(struct intel_dsi * intel_dsi,const u8 * data)461 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
462 {
463 struct drm_device *dev = intel_dsi->base.base.dev;
464 struct drm_i915_private *dev_priv = to_i915(dev);
465 struct intel_connector *connector = intel_dsi->attached_connector;
466 u8 gpio_source, gpio_index = 0, gpio_number;
467 bool value;
468 bool native = DISPLAY_VER(dev_priv) >= 11;
469
470 if (connector->panel.vbt.dsi.seq_version >= 3)
471 gpio_index = *data++;
472
473 gpio_number = *data++;
474
475 /* gpio source in sequence v2 only */
476 if (connector->panel.vbt.dsi.seq_version == 2)
477 gpio_source = (*data >> 1) & 3;
478 else
479 gpio_source = 0;
480
481 if (connector->panel.vbt.dsi.seq_version >= 4 && *data & BIT(1))
482 native = false;
483
484 /* pull up/down */
485 value = *data++ & 1;
486
487 drm_dbg_kms(&dev_priv->drm, "GPIO index %u, number %u, source %u, native %s, set to %s\n",
488 gpio_index, gpio_number, gpio_source, str_yes_no(native), str_on_off(value));
489
490 if (native)
491 icl_native_gpio_set_value(dev_priv, gpio_number, value);
492 else if (DISPLAY_VER(dev_priv) >= 11)
493 icl_exec_gpio(connector, gpio_source, gpio_index, value);
494 else if (IS_VALLEYVIEW(dev_priv))
495 vlv_exec_gpio(connector, gpio_source, gpio_number, value);
496 else if (IS_CHERRYVIEW(dev_priv))
497 chv_exec_gpio(connector, gpio_source, gpio_number, value);
498 else
499 bxt_exec_gpio(connector, gpio_source, gpio_index, value);
500
501 return data;
502 }
503
504 #ifdef CONFIG_ACPI
i2c_adapter_lookup(struct acpi_resource * ares,void * data)505 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data)
506 {
507 struct i2c_adapter_lookup *lookup = data;
508 struct intel_dsi *intel_dsi = lookup->intel_dsi;
509 struct acpi_resource_i2c_serialbus *sb;
510 struct i2c_adapter *adapter;
511 acpi_handle adapter_handle;
512 acpi_status status;
513
514 if (!i2c_acpi_get_i2c_resource(ares, &sb))
515 return 1;
516
517 if (lookup->slave_addr != sb->slave_address)
518 return 1;
519
520 status = acpi_get_handle(lookup->dev_handle,
521 sb->resource_source.string_ptr,
522 &adapter_handle);
523 if (ACPI_FAILURE(status))
524 return 1;
525
526 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle);
527 if (adapter)
528 intel_dsi->i2c_bus_num = adapter->nr;
529
530 return 1;
531 }
532
i2c_acpi_find_adapter(struct intel_dsi * intel_dsi,const u16 slave_addr)533 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
534 const u16 slave_addr)
535 {
536 struct drm_device *drm_dev = intel_dsi->base.base.dev;
537 struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev);
538 struct i2c_adapter_lookup lookup = {
539 .slave_addr = slave_addr,
540 .intel_dsi = intel_dsi,
541 .dev_handle = acpi_device_handle(adev),
542 };
543 LIST_HEAD(resource_list);
544
545 acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup);
546 acpi_dev_free_resource_list(&resource_list);
547 }
548 #else
i2c_acpi_find_adapter(struct intel_dsi * intel_dsi,const u16 slave_addr)549 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
550 const u16 slave_addr)
551 {
552 }
553 #endif
554
mipi_exec_i2c(struct intel_dsi * intel_dsi,const u8 * data)555 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
556 {
557 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
558 struct i2c_adapter *adapter;
559 struct i2c_msg msg;
560 int ret;
561 u8 vbt_i2c_bus_num = *(data + 2);
562 u16 slave_addr = *(u16 *)(data + 3);
563 u8 reg_offset = *(data + 5);
564 u8 payload_size = *(data + 6);
565 u8 *payload_data;
566
567 if (intel_dsi->i2c_bus_num < 0) {
568 intel_dsi->i2c_bus_num = vbt_i2c_bus_num;
569 i2c_acpi_find_adapter(intel_dsi, slave_addr);
570 }
571
572 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num);
573 if (!adapter) {
574 drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n");
575 goto err_bus;
576 }
577
578 payload_data = kzalloc(payload_size + 1, GFP_KERNEL);
579 if (!payload_data)
580 goto err_alloc;
581
582 payload_data[0] = reg_offset;
583 memcpy(&payload_data[1], (data + 7), payload_size);
584
585 msg.addr = slave_addr;
586 msg.flags = 0;
587 msg.len = payload_size + 1;
588 msg.buf = payload_data;
589
590 ret = i2c_transfer(adapter, &msg, 1);
591 if (ret < 0)
592 drm_err(&i915->drm,
593 "Failed to xfer payload of size (%u) to reg (%u)\n",
594 payload_size, reg_offset);
595
596 kfree(payload_data);
597 err_alloc:
598 i2c_put_adapter(adapter);
599 err_bus:
600 return data + payload_size + 7;
601 }
602
mipi_exec_spi(struct intel_dsi * intel_dsi,const u8 * data)603 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
604 {
605 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
606
607 drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n");
608
609 return data + *(data + 5) + 6;
610 }
611
mipi_exec_pmic(struct intel_dsi * intel_dsi,const u8 * data)612 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
613 {
614 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
615 #ifdef CONFIG_PMIC_OPREGION
616 u32 value, mask, reg_address;
617 u16 i2c_address;
618 int ret;
619
620 /* byte 0 aka PMIC Flag is reserved */
621 i2c_address = get_unaligned_le16(data + 1);
622 reg_address = get_unaligned_le32(data + 3);
623 value = get_unaligned_le32(data + 7);
624 mask = get_unaligned_le32(data + 11);
625
626 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address,
627 reg_address,
628 value, mask);
629 if (ret)
630 drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret);
631 #else
632 drm_err(&i915->drm,
633 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n");
634 #endif
635
636 return data + 15;
637 }
638
639 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
640 const u8 *data);
641 static const fn_mipi_elem_exec exec_elem[] = {
642 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
643 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
644 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
645 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
646 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
647 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
648 };
649
650 /*
651 * MIPI Sequence from VBT #53 parsing logic
652 * We have already separated each seqence during bios parsing
653 * Following is generic execution function for any sequence
654 */
655
656 static const char * const seq_name[] = {
657 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
658 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
659 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
660 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF",
661 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
662 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
663 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
664 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
665 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
666 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
667 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
668 };
669
sequence_name(enum mipi_seq seq_id)670 static const char *sequence_name(enum mipi_seq seq_id)
671 {
672 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
673 return seq_name[seq_id];
674 else
675 return "(unknown)";
676 }
677
intel_dsi_vbt_exec(struct intel_dsi * intel_dsi,enum mipi_seq seq_id)678 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
679 enum mipi_seq seq_id)
680 {
681 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
682 struct intel_connector *connector = intel_dsi->attached_connector;
683 const u8 *data;
684 fn_mipi_elem_exec mipi_elem_exec;
685
686 if (drm_WARN_ON(&dev_priv->drm,
687 seq_id >= ARRAY_SIZE(connector->panel.vbt.dsi.sequence)))
688 return;
689
690 data = connector->panel.vbt.dsi.sequence[seq_id];
691 if (!data)
692 return;
693
694 drm_WARN_ON(&dev_priv->drm, *data != seq_id);
695
696 drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n",
697 seq_id, sequence_name(seq_id));
698
699 /* Skip Sequence Byte. */
700 data++;
701
702 /* Skip Size of Sequence. */
703 if (connector->panel.vbt.dsi.seq_version >= 3)
704 data += 4;
705
706 while (1) {
707 u8 operation_byte = *data++;
708 u8 operation_size = 0;
709
710 if (operation_byte == MIPI_SEQ_ELEM_END)
711 break;
712
713 if (operation_byte < ARRAY_SIZE(exec_elem))
714 mipi_elem_exec = exec_elem[operation_byte];
715 else
716 mipi_elem_exec = NULL;
717
718 /* Size of Operation. */
719 if (connector->panel.vbt.dsi.seq_version >= 3)
720 operation_size = *data++;
721
722 if (mipi_elem_exec) {
723 const u8 *next = data + operation_size;
724
725 data = mipi_elem_exec(intel_dsi, data);
726
727 /* Consistency check if we have size. */
728 if (operation_size && data != next) {
729 drm_err(&dev_priv->drm,
730 "Inconsistent operation size\n");
731 return;
732 }
733 } else if (operation_size) {
734 /* We have size, skip. */
735 drm_dbg_kms(&dev_priv->drm,
736 "Unsupported MIPI operation byte %u\n",
737 operation_byte);
738 data += operation_size;
739 } else {
740 /* No size, can't skip without parsing. */
741 drm_err(&dev_priv->drm,
742 "Unsupported MIPI operation byte %u\n",
743 operation_byte);
744 return;
745 }
746 }
747 }
748
intel_dsi_vbt_exec_sequence(struct intel_dsi * intel_dsi,enum mipi_seq seq_id)749 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
750 enum mipi_seq seq_id)
751 {
752 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel)
753 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
754 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight)
755 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1);
756
757 intel_dsi_vbt_exec(intel_dsi, seq_id);
758
759 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel)
760 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
761 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight)
762 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0);
763 }
764
intel_dsi_msleep(struct intel_dsi * intel_dsi,int msec)765 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
766 {
767 struct intel_connector *connector = intel_dsi->attached_connector;
768
769 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
770 if (is_vid_mode(intel_dsi) && connector->panel.vbt.dsi.seq_version >= 3)
771 return;
772
773 msleep(msec);
774 }
775
intel_dsi_log_params(struct intel_dsi * intel_dsi)776 void intel_dsi_log_params(struct intel_dsi *intel_dsi)
777 {
778 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
779
780 drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk);
781 drm_dbg_kms(&i915->drm, "Pixel overlap %d\n",
782 intel_dsi->pixel_overlap);
783 drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count);
784 drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
785 drm_dbg_kms(&i915->drm, "Video mode format %s\n",
786 intel_dsi->video_mode == NON_BURST_SYNC_PULSE ?
787 "non-burst with sync pulse" :
788 intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ?
789 "non-burst with sync events" :
790 intel_dsi->video_mode == BURST_MODE ?
791 "burst" : "<unknown>");
792 drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n",
793 intel_dsi->burst_mode_ratio);
794 drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val);
795 drm_dbg_kms(&i915->drm, "Eot %s\n",
796 str_enabled_disabled(intel_dsi->eotp_pkt));
797 drm_dbg_kms(&i915->drm, "Clockstop %s\n",
798 str_enabled_disabled(!intel_dsi->clock_stop));
799 drm_dbg_kms(&i915->drm, "Mode %s\n",
800 intel_dsi->operation_mode ? "command" : "video");
801 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
802 drm_dbg_kms(&i915->drm,
803 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
804 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
805 drm_dbg_kms(&i915->drm,
806 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
807 else
808 drm_dbg_kms(&i915->drm, "Dual link: NONE\n");
809 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format);
810 drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div);
811 drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n",
812 intel_dsi->lp_rx_timeout);
813 drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n",
814 intel_dsi->turn_arnd_val);
815 drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count);
816 drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n",
817 intel_dsi->hs_to_lp_count);
818 drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
819 drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
820 drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n",
821 intel_dsi->clk_lp_to_hs_count);
822 drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n",
823 intel_dsi->clk_hs_to_lp_count);
824 drm_dbg_kms(&i915->drm, "BTA %s\n",
825 str_enabled_disabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
826 }
827
intel_dsi_vbt_init(struct intel_dsi * intel_dsi,u16 panel_id)828 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
829 {
830 struct drm_device *dev = intel_dsi->base.base.dev;
831 struct drm_i915_private *dev_priv = to_i915(dev);
832 struct intel_connector *connector = intel_dsi->attached_connector;
833 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
834 struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps;
835 struct drm_display_mode *mode = connector->panel.vbt.lfp_lvds_vbt_mode;
836 u16 burst_mode_ratio;
837 enum port port;
838
839 drm_dbg_kms(&dev_priv->drm, "\n");
840
841 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
842 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
843 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
844 intel_dsi->pixel_format =
845 pixel_format_from_register_bits(
846 mipi_config->videomode_color_format << 7);
847
848 intel_dsi->dual_link = mipi_config->dual_link;
849 intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
850 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
851 intel_dsi->video_mode = mipi_config->video_transfer_mode;
852 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
853 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
854 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
855 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
856 intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
857 intel_dsi->init_count = mipi_config->master_init_timer;
858 intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
859 intel_dsi->video_frmt_cfg_bits =
860 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
861 intel_dsi->bgr_enabled = mipi_config->rgb_flip;
862
863 /* Starting point, adjusted depending on dual link and burst mode */
864 intel_dsi->pclk = mode->clock;
865
866 /* In dual link mode each port needs half of pixel clock */
867 if (intel_dsi->dual_link) {
868 intel_dsi->pclk /= 2;
869
870 /* we can enable pixel_overlap if needed by panel. In this
871 * case we need to increase the pixelclock for extra pixels
872 */
873 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
874 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
875 }
876 }
877
878 /* Burst Mode Ratio
879 * Target ddr frequency from VBT / non burst ddr freq
880 * multiply by 100 to preserve remainder
881 */
882 if (intel_dsi->video_mode == BURST_MODE) {
883 if (mipi_config->target_burst_mode_freq) {
884 u32 bitrate = intel_dsi_bitrate(intel_dsi);
885
886 /*
887 * Sometimes the VBT contains a slightly lower clock,
888 * then the bitrate we have calculated, in this case
889 * just replace it with the calculated bitrate.
890 */
891 if (mipi_config->target_burst_mode_freq < bitrate &&
892 intel_fuzzy_clock_check(
893 mipi_config->target_burst_mode_freq,
894 bitrate))
895 mipi_config->target_burst_mode_freq = bitrate;
896
897 if (mipi_config->target_burst_mode_freq < bitrate) {
898 drm_err(&dev_priv->drm,
899 "Burst mode freq is less than computed\n");
900 return false;
901 }
902
903 burst_mode_ratio = DIV_ROUND_UP(
904 mipi_config->target_burst_mode_freq * 100,
905 bitrate);
906
907 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
908 } else {
909 drm_err(&dev_priv->drm,
910 "Burst mode target is not set\n");
911 return false;
912 }
913 } else
914 burst_mode_ratio = 100;
915
916 intel_dsi->burst_mode_ratio = burst_mode_ratio;
917
918 /* delays in VBT are in unit of 100us, so need to convert
919 * here in ms
920 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
921 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
922 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
923 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
924 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
925 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
926
927 intel_dsi->i2c_bus_num = -1;
928
929 /* a regular driver would get the device in probe */
930 for_each_dsi_port(port, intel_dsi->ports) {
931 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
932 }
933
934 return true;
935 }
936
937 /*
938 * On some BYT/CHT devs some sequences are incomplete and we need to manually
939 * control some GPIOs. We need to add a GPIO lookup table before we get these.
940 * If the GOP did not initialize the panel (HDMI inserted) we may need to also
941 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM.
942 */
943 static struct gpiod_lookup_table pmic_panel_gpio_table = {
944 /* Intel GFX is consumer */
945 .dev_id = "0000:00:02.0",
946 .table = {
947 /* Panel EN/DISABLE */
948 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH),
949 { }
950 },
951 };
952
953 static struct gpiod_lookup_table soc_panel_gpio_table = {
954 .dev_id = "0000:00:02.0",
955 .table = {
956 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH),
957 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH),
958 { }
959 },
960 };
961
962 static const struct pinctrl_map soc_pwm_pinctrl_map[] = {
963 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00",
964 "pwm0_grp", "pwm"),
965 };
966
intel_dsi_vbt_gpio_init(struct intel_dsi * intel_dsi,bool panel_is_on)967 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)
968 {
969 struct drm_device *dev = intel_dsi->base.base.dev;
970 struct drm_i915_private *dev_priv = to_i915(dev);
971 struct intel_connector *connector = intel_dsi->attached_connector;
972 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
973 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
974 bool want_backlight_gpio = false;
975 bool want_panel_gpio = false;
976 struct pinctrl *pinctrl;
977 int ret;
978
979 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
980 mipi_config->pwm_blc == PPS_BLC_PMIC) {
981 gpiod_add_lookup_table(&pmic_panel_gpio_table);
982 want_panel_gpio = true;
983 }
984
985 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
986 gpiod_add_lookup_table(&soc_panel_gpio_table);
987 want_panel_gpio = true;
988 want_backlight_gpio = true;
989
990 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */
991 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map,
992 ARRAY_SIZE(soc_pwm_pinctrl_map));
993 if (ret)
994 drm_err(&dev_priv->drm,
995 "Failed to register pwm0 pinmux mapping\n");
996
997 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0");
998 if (IS_ERR(pinctrl))
999 drm_err(&dev_priv->drm,
1000 "Failed to set pinmux to PWM\n");
1001 }
1002
1003 if (want_panel_gpio) {
1004 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags);
1005 if (IS_ERR(intel_dsi->gpio_panel)) {
1006 drm_err(&dev_priv->drm,
1007 "Failed to own gpio for panel control\n");
1008 intel_dsi->gpio_panel = NULL;
1009 }
1010 }
1011
1012 if (want_backlight_gpio) {
1013 intel_dsi->gpio_backlight =
1014 gpiod_get(dev->dev, "backlight", flags);
1015 if (IS_ERR(intel_dsi->gpio_backlight)) {
1016 drm_err(&dev_priv->drm,
1017 "Failed to own gpio for backlight control\n");
1018 intel_dsi->gpio_backlight = NULL;
1019 }
1020 }
1021 }
1022
intel_dsi_vbt_gpio_cleanup(struct intel_dsi * intel_dsi)1023 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi)
1024 {
1025 struct drm_device *dev = intel_dsi->base.base.dev;
1026 struct drm_i915_private *dev_priv = to_i915(dev);
1027 struct intel_connector *connector = intel_dsi->attached_connector;
1028 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1029
1030 if (intel_dsi->gpio_panel) {
1031 gpiod_put(intel_dsi->gpio_panel);
1032 intel_dsi->gpio_panel = NULL;
1033 }
1034
1035 if (intel_dsi->gpio_backlight) {
1036 gpiod_put(intel_dsi->gpio_backlight);
1037 intel_dsi->gpio_backlight = NULL;
1038 }
1039
1040 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1041 mipi_config->pwm_blc == PPS_BLC_PMIC)
1042 gpiod_remove_lookup_table(&pmic_panel_gpio_table);
1043
1044 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
1045 pinctrl_unregister_mappings(soc_pwm_pinctrl_map);
1046 gpiod_remove_lookup_table(&soc_panel_gpio_table);
1047 }
1048 }
1049