Searched refs:IA_CSS_PIPE_ID_NUM (Results 1 – 12 of 12) sorted by relevance
78 struct ia_css_dp_config pipe_dp_config[IA_CSS_PIPE_ID_NUM];107 struct ia_css_dvs_6axis_config *pipe_dvs_6axis_config[IA_CSS_PIPE_ID_NUM];117 [IA_CSS_PIPE_ID_NUM][SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES];131 bool pipe_dpc_config_changed[IA_CSS_PIPE_ID_NUM];135 bool pipe_dvs_6axis_config_changed[IA_CSS_PIPE_ID_NUM];141 struct sh_css_ddr_address_map pipe_ddr_ptrs[IA_CSS_PIPE_ID_NUM];142 struct sh_css_ddr_address_map_size pipe_ddr_ptrs_size[IA_CSS_PIPE_ID_NUM];
68 struct ia_css_pipe *pipes[IA_CSS_PIPE_ID_NUM];69 struct ia_css_pipe *multi_pipes[IA_CSS_PIPE_ID_NUM];70 struct ia_css_pipe_config pipe_configs[IA_CSS_PIPE_ID_NUM];71 struct ia_css_pipe_extra_config pipe_extra_configs[IA_CSS_PIPE_ID_NUM];72 bool update_pipe[IA_CSS_PIPE_ID_NUM];
36 IA_CSS_PIPE_ID_NUM enumerator
287 unsigned int s3a_bufs_in_css[IA_CSS_PIPE_ID_NUM];291 [ATOMISP_INPUT_STREAM_NUM][IA_CSS_PIPE_ID_NUM];
294 for (j = 0; j < IA_CSS_PIPE_ID_NUM; j++) { in __dump_stream_config()479 struct ia_css_pipe *multi_pipes[IA_CSS_PIPE_ID_NUM]; in __create_stream()481 for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { in __create_stream()533 for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { in __destroy_stream_pipes()586 if (pipe_id < 0 || pipe_id >= IA_CSS_PIPE_ID_NUM) { in __apply_additional_pipe_config()718 if (pipe_id >= IA_CSS_PIPE_ID_NUM) in __create_pipe()757 for (j = 0; j < IA_CSS_PIPE_ID_NUM; j++) { in __create_pipes()762 if (j < IA_CSS_PIPE_ID_NUM) in __create_pipes()774 j = IA_CSS_PIPE_ID_NUM; in __create_pipes()1452 if (asd->params.s3a_enabled_pipe != IA_CSS_PIPE_ID_NUM) in atomisp_css_get_grid_info()[all …]
222 if (WARN_ON(css_pipe_id >= IA_CSS_PIPE_ID_NUM)) in atomisp_q_video_buffers_to_css()376 enum ia_css_pipe_id css_capture_pipe_id = IA_CSS_PIPE_ID_NUM; in atomisp_qbuffers_to_css()377 enum ia_css_pipe_id css_preview_pipe_id = IA_CSS_PIPE_ID_NUM; in atomisp_qbuffers_to_css()378 enum ia_css_pipe_id css_video_pipe_id = IA_CSS_PIPE_ID_NUM; in atomisp_qbuffers_to_css()615 asd->params.s3a_enabled_pipe = IA_CSS_PIPE_ID_NUM; in atomisp_subdev_init_struct()
120 static ia_css_ptr xmem_sp_stage_ptrs[IA_CSS_PIPE_ID_NUM]122 static ia_css_ptr xmem_isp_stage_ptrs[IA_CSS_PIPE_ID_NUM]1661 assert(pipe->mode < IA_CSS_PIPE_ID_NUM); in sh_css_set_pipe_dvs_6axis_config()1686 if ((pipe->mode < IA_CSS_PIPE_ID_NUM) && in sh_css_get_pipe_dvs_6axis_config()1941 for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { in sh_css_set_per_frame_isp_config_on_pipe()1981 if ((pipe->mode < IA_CSS_PIPE_ID_NUM) && in sh_css_init_isp_params_from_config()2290 for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { in ia_css_stream_isp_parameters_init()2348 for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { in sh_css_create_isp_params()2544 for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { in sh_css_init_isp_params_from_global()2578 for (p = 0; p < IA_CSS_PIPE_ID_NUM; p++) { in sh_css_params_init()[all …]
1543 for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { in sh_css_event_init_irq_mask()1565 assert(IA_CSS_PIPE_ID_NUM == NR_OF_PIPELINES); in ia_css_pipe_set_irq_mask()1581 if (pipe_num >= IA_CSS_PIPE_ID_NUM) in ia_css_pipe_set_irq_mask()1608 assert(IA_CSS_PIPE_ID_NUM == NR_OF_PIPELINES); in ia_css_event_get_irq_mask()1611 if (pipe_num >= IA_CSS_PIPE_ID_NUM) in ia_css_event_get_irq_mask()
84 #define NR_OF_PIPELINES IA_CSS_PIPE_ID_NUM /* Must match with IA_CSS_PIPE_ID_NUM */
138 struct ia_css_pipe *pipes[IA_CSS_PIPE_ID_NUM];139 struct ia_css_pipe **orig_pipes[IA_CSS_PIPE_ID_NUM];140 struct ia_css_pipe_config pipe_config[IA_CSS_PIPE_ID_NUM];3818 assert(pipe_id < IA_CSS_PIPE_ID_NUM); in ia_css_pipe_enqueue_buffer()3822 pipe_id >= IA_CSS_PIPE_ID_NUM) { in ia_css_pipe_enqueue_buffer()
4847 for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) in atomisp_set_fmt_to_isp()
169 if ((!val) || (key >= IA_CSS_PIPELINE_NUM_MAX) || (key >= IA_CSS_PIPE_ID_NUM)) { in ia_css_pipeline_get_sp_thread_id()470 if ((key >= IA_CSS_PIPELINE_NUM_MAX) || (key >= IA_CSS_PIPE_ID_NUM)) { in ia_css_pipeline_is_mapped()