Searched refs:HSIO (Results 1 – 9 of 9) sorted by relevance
| /linux-6.1.9/Documentation/devicetree/bindings/phy/ |
| D | phy-tegra194-p2u.yaml | 13 Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
15 Tegra234 has three PHY bricks namely HSIO, NVHS and GBE (Gigabit Ethernet)
18 interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one
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| D | mscc,vsc7514-serdes.yaml | 14 On Microsemi Ocelot, there is a handful of registers in HSIO address
29 This is a child of the HSIO syscon ("mscc,ocelot-hsio", see
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| D | intel,combo-phy.yaml | 60 - description: phandle to HSIO registers
62 description: HSIO registers handle and ComboPhy instance id on NOC
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| D | microchip,lan966x-serdes.yaml | 34 - description: HSIO registers
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| /linux-6.1.9/Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx8mp-hsio-blk-ctrl.yaml | 7 title: NXP i.MX8MP HSIO blk-ctrl
13 The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to
15 (USB an PCIe) peripherals located in the HSIO domain of the SoC.
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| /linux-6.1.9/Documentation/devicetree/bindings/mips/ |
| D | mscc.txt | 45 o HSIO regs:
47 The SoC has a few registers (HSIO) handling miscellaneous functionalities:
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| /linux-6.1.9/drivers/net/ethernet/mscc/ |
| D | ocelot_vsc7514.c | 112 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, in ocelot_pll5_init()
115 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, in ocelot_pll5_init()
127 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, in ocelot_pll5_init()
527 ocelot->targets[HSIO] = hsio; in mscc_ocelot_probe()
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| /linux-6.1.9/Documentation/devicetree/bindings/usb/ |
| D | fsl,imx8mp-dwc3.yaml | 19 - description: Address and length of the register set for HSIO Block Control
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| /linux-6.1.9/include/soc/mscc/ |
| D | ocelot.h | 117 HSIO, enumerator
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