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Searched refs:HHI_HDMI_PHY_CNTL1 (Results 1 – 3 of 3) sorted by relevance

/linux-6.1.9/drivers/phy/amlogic/
Dphy-meson8-hdmi-tx.c29 #define HHI_HDMI_PHY_CNTL1 0x3a4 macro
71 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, 0x0); in phy_meson8_hdmi_tx_power_on()
75 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, in phy_meson8_hdmi_tx_power_on()
80 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, in phy_meson8_hdmi_tx_power_on()
/linux-6.1.9/drivers/gpu/drm/meson/
Dmeson_dw_hdmi.c107 #define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */ macro
358 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xf); in meson_dw_hdmi_phy_reset()
363 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xe); in meson_dw_hdmi_phy_reset()
429 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, in dw_hdmi_phy_init()
436 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, in dw_hdmi_phy_init()
439 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, in dw_hdmi_phy_init()
443 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0); in dw_hdmi_phy_init()
/linux-6.1.9/drivers/clk/meson/
Dgxbb.h107 #define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */ macro