1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3 
4 #ifndef __HCLGE_MAIN_H
5 #define __HCLGE_MAIN_H
6 #include <linux/fs.h>
7 #include <linux/types.h>
8 #include <linux/phy.h>
9 #include <linux/if_vlan.h>
10 #include <linux/kfifo.h>
11 #include <net/devlink.h>
12 
13 #include "hclge_cmd.h"
14 #include "hclge_ptp.h"
15 #include "hnae3.h"
16 #include "hclge_comm_rss.h"
17 #include "hclge_comm_tqp_stats.h"
18 
19 #define HCLGE_MOD_VERSION "1.0"
20 #define HCLGE_DRIVER_NAME "hclge"
21 
22 #define HCLGE_MAX_PF_NUM		8
23 
24 #define HCLGE_VF_VPORT_START_NUM	1
25 
26 #define HCLGE_RD_FIRST_STATS_NUM        2
27 #define HCLGE_RD_OTHER_STATS_NUM        4
28 
29 #define HCLGE_INVALID_VPORT 0xffff
30 
31 #define HCLGE_PF_CFG_BLOCK_SIZE		32
32 #define HCLGE_PF_CFG_DESC_NUM \
33 	(HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
34 
35 #define HCLGE_VECTOR_REG_BASE		0x20000
36 #define HCLGE_VECTOR_EXT_REG_BASE	0x30000
37 #define HCLGE_MISC_VECTOR_REG_BASE	0x20400
38 
39 #define HCLGE_VECTOR_REG_OFFSET		0x4
40 #define HCLGE_VECTOR_REG_OFFSET_H	0x1000
41 #define HCLGE_VECTOR_VF_OFFSET		0x100000
42 
43 #define HCLGE_NIC_CSQ_DEPTH_REG		0x27008
44 
45 /* bar registers for common func */
46 #define HCLGE_GRO_EN_REG		0x28000
47 #define HCLGE_RXD_ADV_LAYOUT_EN_REG	0x28008
48 
49 /* bar registers for rcb */
50 #define HCLGE_RING_RX_ADDR_L_REG	0x80000
51 #define HCLGE_RING_RX_ADDR_H_REG	0x80004
52 #define HCLGE_RING_RX_BD_NUM_REG	0x80008
53 #define HCLGE_RING_RX_BD_LENGTH_REG	0x8000C
54 #define HCLGE_RING_RX_MERGE_EN_REG	0x80014
55 #define HCLGE_RING_RX_TAIL_REG		0x80018
56 #define HCLGE_RING_RX_HEAD_REG		0x8001C
57 #define HCLGE_RING_RX_FBD_NUM_REG	0x80020
58 #define HCLGE_RING_RX_OFFSET_REG	0x80024
59 #define HCLGE_RING_RX_FBD_OFFSET_REG	0x80028
60 #define HCLGE_RING_RX_STASH_REG		0x80030
61 #define HCLGE_RING_RX_BD_ERR_REG	0x80034
62 #define HCLGE_RING_TX_ADDR_L_REG	0x80040
63 #define HCLGE_RING_TX_ADDR_H_REG	0x80044
64 #define HCLGE_RING_TX_BD_NUM_REG	0x80048
65 #define HCLGE_RING_TX_PRIORITY_REG	0x8004C
66 #define HCLGE_RING_TX_TC_REG		0x80050
67 #define HCLGE_RING_TX_MERGE_EN_REG	0x80054
68 #define HCLGE_RING_TX_TAIL_REG		0x80058
69 #define HCLGE_RING_TX_HEAD_REG		0x8005C
70 #define HCLGE_RING_TX_FBD_NUM_REG	0x80060
71 #define HCLGE_RING_TX_OFFSET_REG	0x80064
72 #define HCLGE_RING_TX_EBD_NUM_REG	0x80068
73 #define HCLGE_RING_TX_EBD_OFFSET_REG	0x80070
74 #define HCLGE_RING_TX_BD_ERR_REG	0x80074
75 #define HCLGE_RING_EN_REG		0x80090
76 
77 /* bar registers for tqp interrupt */
78 #define HCLGE_TQP_INTR_CTRL_REG		0x20000
79 #define HCLGE_TQP_INTR_GL0_REG		0x20100
80 #define HCLGE_TQP_INTR_GL1_REG		0x20200
81 #define HCLGE_TQP_INTR_GL2_REG		0x20300
82 #define HCLGE_TQP_INTR_RL_REG		0x20900
83 
84 #define HCLGE_RSS_IND_TBL_SIZE		512
85 
86 #define HCLGE_RSS_TC_SIZE_0		1
87 #define HCLGE_RSS_TC_SIZE_1		2
88 #define HCLGE_RSS_TC_SIZE_2		4
89 #define HCLGE_RSS_TC_SIZE_3		8
90 #define HCLGE_RSS_TC_SIZE_4		16
91 #define HCLGE_RSS_TC_SIZE_5		32
92 #define HCLGE_RSS_TC_SIZE_6		64
93 #define HCLGE_RSS_TC_SIZE_7		128
94 
95 #define HCLGE_UMV_TBL_SIZE		3072
96 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \
97 	(HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM)
98 
99 #define HCLGE_TQP_RESET_TRY_TIMES	200
100 
101 #define HCLGE_PHY_PAGE_MDIX		0
102 #define HCLGE_PHY_PAGE_COPPER		0
103 
104 /* Page Selection Reg. */
105 #define HCLGE_PHY_PAGE_REG		22
106 
107 /* Copper Specific Control Register */
108 #define HCLGE_PHY_CSC_REG		16
109 
110 /* Copper Specific Status Register */
111 #define HCLGE_PHY_CSS_REG		17
112 
113 #define HCLGE_PHY_MDIX_CTRL_S		5
114 #define HCLGE_PHY_MDIX_CTRL_M		GENMASK(6, 5)
115 
116 #define HCLGE_PHY_MDIX_STATUS_B		6
117 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B	11
118 
119 #define HCLGE_GET_DFX_REG_TYPE_CNT	4
120 
121 /* Factor used to calculate offset and bitmap of VF num */
122 #define HCLGE_VF_NUM_PER_CMD           64
123 
124 #define HCLGE_MAX_QSET_NUM		1024
125 
126 #define HCLGE_DBG_RESET_INFO_LEN	1024
127 
128 enum HLCGE_PORT_TYPE {
129 	HOST_PORT,
130 	NETWORK_PORT
131 };
132 
133 #define PF_VPORT_ID			0
134 
135 #define HCLGE_PF_ID_S			0
136 #define HCLGE_PF_ID_M			GENMASK(2, 0)
137 #define HCLGE_VF_ID_S			3
138 #define HCLGE_VF_ID_M			GENMASK(10, 3)
139 #define HCLGE_PORT_TYPE_B		11
140 #define HCLGE_NETWORK_PORT_ID_S		0
141 #define HCLGE_NETWORK_PORT_ID_M		GENMASK(3, 0)
142 
143 /* Reset related Registers */
144 #define HCLGE_PF_OTHER_INT_REG		0x20600
145 #define HCLGE_MISC_RESET_STS_REG	0x20700
146 #define HCLGE_MISC_VECTOR_INT_STS	0x20800
147 #define HCLGE_GLOBAL_RESET_REG		0x20A00
148 #define HCLGE_GLOBAL_RESET_BIT		0
149 #define HCLGE_CORE_RESET_BIT		1
150 #define HCLGE_IMP_RESET_BIT		2
151 #define HCLGE_RESET_INT_M		GENMASK(7, 5)
152 #define HCLGE_FUN_RST_ING		0x20C00
153 #define HCLGE_FUN_RST_ING_B		0
154 
155 /* Vector0 register bits define */
156 #define HCLGE_VECTOR0_REG_PTP_INT_B	0
157 #define HCLGE_VECTOR0_GLOBALRESET_INT_B	5
158 #define HCLGE_VECTOR0_CORERESET_INT_B	6
159 #define HCLGE_VECTOR0_IMPRESET_INT_B	7
160 
161 /* Vector0 interrupt CMDQ event source register(RW) */
162 #define HCLGE_VECTOR0_CMDQ_SRC_REG	0x27100
163 /* CMDQ register bits for RX event(=MBX event) */
164 #define HCLGE_VECTOR0_RX_CMDQ_INT_B	1
165 
166 #define HCLGE_VECTOR0_IMP_RESET_INT_B	1
167 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B	4U
168 #define HCLGE_VECTOR0_IMP_RD_POISON_B	5U
169 #define HCLGE_VECTOR0_ALL_MSIX_ERR_B	6U
170 #define HCLGE_TRIGGER_IMP_RESET_B	7U
171 
172 #define HCLGE_TQP_MEM_SIZE		0x10000
173 #define HCLGE_MEM_BAR			4
174 /* in the bar4, the first half is for roce, and the second half is for nic */
175 #define HCLGE_NIC_MEM_OFFSET(hdev)	\
176 	(pci_resource_len((hdev)->pdev, HCLGE_MEM_BAR) >> 1)
177 #define HCLGE_TQP_MEM_OFFSET(hdev, i)	\
178 	(HCLGE_NIC_MEM_OFFSET(hdev) + HCLGE_TQP_MEM_SIZE * (i))
179 
180 #define HCLGE_MAC_DEFAULT_FRAME \
181 	(ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
182 #define HCLGE_MAC_MIN_FRAME		64
183 #define HCLGE_MAC_MAX_FRAME		9728
184 
185 #define HCLGE_SUPPORT_1G_BIT		BIT(0)
186 #define HCLGE_SUPPORT_10G_BIT		BIT(1)
187 #define HCLGE_SUPPORT_25G_BIT		BIT(2)
188 #define HCLGE_SUPPORT_50G_BIT		BIT(3)
189 #define HCLGE_SUPPORT_100G_BIT		BIT(4)
190 /* to be compatible with exsit board */
191 #define HCLGE_SUPPORT_40G_BIT		BIT(5)
192 #define HCLGE_SUPPORT_100M_BIT		BIT(6)
193 #define HCLGE_SUPPORT_10M_BIT		BIT(7)
194 #define HCLGE_SUPPORT_200G_BIT		BIT(8)
195 #define HCLGE_SUPPORT_GE \
196 	(HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)
197 
198 enum HCLGE_DEV_STATE {
199 	HCLGE_STATE_REINITING,
200 	HCLGE_STATE_DOWN,
201 	HCLGE_STATE_DISABLED,
202 	HCLGE_STATE_REMOVING,
203 	HCLGE_STATE_NIC_REGISTERED,
204 	HCLGE_STATE_ROCE_REGISTERED,
205 	HCLGE_STATE_SERVICE_INITED,
206 	HCLGE_STATE_RST_SERVICE_SCHED,
207 	HCLGE_STATE_RST_HANDLING,
208 	HCLGE_STATE_MBX_SERVICE_SCHED,
209 	HCLGE_STATE_MBX_HANDLING,
210 	HCLGE_STATE_ERR_SERVICE_SCHED,
211 	HCLGE_STATE_STATISTICS_UPDATING,
212 	HCLGE_STATE_LINK_UPDATING,
213 	HCLGE_STATE_RST_FAIL,
214 	HCLGE_STATE_FD_TBL_CHANGED,
215 	HCLGE_STATE_FD_CLEAR_ALL,
216 	HCLGE_STATE_FD_USER_DEF_CHANGED,
217 	HCLGE_STATE_PTP_EN,
218 	HCLGE_STATE_PTP_TX_HANDLING,
219 	HCLGE_STATE_FEC_STATS_UPDATING,
220 	HCLGE_STATE_MAX
221 };
222 
223 enum hclge_evt_cause {
224 	HCLGE_VECTOR0_EVENT_RST,
225 	HCLGE_VECTOR0_EVENT_MBX,
226 	HCLGE_VECTOR0_EVENT_ERR,
227 	HCLGE_VECTOR0_EVENT_PTP,
228 	HCLGE_VECTOR0_EVENT_OTHER,
229 };
230 
231 enum HCLGE_MAC_SPEED {
232 	HCLGE_MAC_SPEED_UNKNOWN = 0,		/* unknown */
233 	HCLGE_MAC_SPEED_10M	= 10,		/* 10 Mbps */
234 	HCLGE_MAC_SPEED_100M	= 100,		/* 100 Mbps */
235 	HCLGE_MAC_SPEED_1G	= 1000,		/* 1000 Mbps   = 1 Gbps */
236 	HCLGE_MAC_SPEED_10G	= 10000,	/* 10000 Mbps  = 10 Gbps */
237 	HCLGE_MAC_SPEED_25G	= 25000,	/* 25000 Mbps  = 25 Gbps */
238 	HCLGE_MAC_SPEED_40G	= 40000,	/* 40000 Mbps  = 40 Gbps */
239 	HCLGE_MAC_SPEED_50G	= 50000,	/* 50000 Mbps  = 50 Gbps */
240 	HCLGE_MAC_SPEED_100G	= 100000,	/* 100000 Mbps = 100 Gbps */
241 	HCLGE_MAC_SPEED_200G	= 200000	/* 200000 Mbps = 200 Gbps */
242 };
243 
244 enum HCLGE_MAC_DUPLEX {
245 	HCLGE_MAC_HALF,
246 	HCLGE_MAC_FULL
247 };
248 
249 #define QUERY_SFP_SPEED		0
250 #define QUERY_ACTIVE_SPEED	1
251 
252 struct hclge_mac {
253 	u8 mac_id;
254 	u8 phy_addr;
255 	u8 flag;
256 	u8 media_type;	/* port media type, e.g. fibre/copper/backplane */
257 	u8 mac_addr[ETH_ALEN];
258 	u8 autoneg;
259 	u8 duplex;
260 	u8 support_autoneg;
261 	u8 speed_type;	/* 0: sfp speed, 1: active speed */
262 	u8 lane_num;
263 	u32 speed;
264 	u32 max_speed;
265 	u32 speed_ability; /* speed ability supported by current media */
266 	u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */
267 	u32 fec_mode; /* active fec mode */
268 	u32 user_fec_mode;
269 	u32 fec_ability;
270 	int link;	/* store the link status of mac & phy (if phy exists) */
271 	struct phy_device *phydev;
272 	struct mii_bus *mdio_bus;
273 	phy_interface_t phy_if;
274 	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
275 	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
276 };
277 
278 struct hclge_hw {
279 	struct hclge_comm_hw hw;
280 	struct hclge_mac mac;
281 	int num_vec;
282 };
283 
284 enum hclge_fc_mode {
285 	HCLGE_FC_NONE,
286 	HCLGE_FC_RX_PAUSE,
287 	HCLGE_FC_TX_PAUSE,
288 	HCLGE_FC_FULL,
289 	HCLGE_FC_PFC,
290 	HCLGE_FC_DEFAULT
291 };
292 
293 #define HCLGE_FILTER_TYPE_VF		0
294 #define HCLGE_FILTER_TYPE_PORT		1
295 #define HCLGE_FILTER_FE_EGRESS_V1_B	BIT(0)
296 #define HCLGE_FILTER_FE_NIC_INGRESS_B	BIT(0)
297 #define HCLGE_FILTER_FE_NIC_EGRESS_B	BIT(1)
298 #define HCLGE_FILTER_FE_ROCE_INGRESS_B	BIT(2)
299 #define HCLGE_FILTER_FE_ROCE_EGRESS_B	BIT(3)
300 #define HCLGE_FILTER_FE_EGRESS		(HCLGE_FILTER_FE_NIC_EGRESS_B \
301 					| HCLGE_FILTER_FE_ROCE_EGRESS_B)
302 #define HCLGE_FILTER_FE_INGRESS		(HCLGE_FILTER_FE_NIC_INGRESS_B \
303 					| HCLGE_FILTER_FE_ROCE_INGRESS_B)
304 
305 enum hclge_vlan_fltr_cap {
306 	HCLGE_VLAN_FLTR_DEF,
307 	HCLGE_VLAN_FLTR_CAN_MDF,
308 };
309 enum hclge_link_fail_code {
310 	HCLGE_LF_NORMAL,
311 	HCLGE_LF_REF_CLOCK_LOST,
312 	HCLGE_LF_XSFP_TX_DISABLE,
313 	HCLGE_LF_XSFP_ABSENT,
314 };
315 
316 #define HCLGE_LINK_STATUS_DOWN 0
317 #define HCLGE_LINK_STATUS_UP   1
318 
319 #define HCLGE_PG_NUM		4
320 #define HCLGE_SCH_MODE_SP	0
321 #define HCLGE_SCH_MODE_DWRR	1
322 struct hclge_pg_info {
323 	u8 pg_id;
324 	u8 pg_sch_mode;		/* 0: sp; 1: dwrr */
325 	u8 tc_bit_map;
326 	u32 bw_limit;
327 	u8 tc_dwrr[HNAE3_MAX_TC];
328 };
329 
330 struct hclge_tc_info {
331 	u8 tc_id;
332 	u8 tc_sch_mode;		/* 0: sp; 1: dwrr */
333 	u8 pgid;
334 	u32 bw_limit;
335 };
336 
337 struct hclge_cfg {
338 	u8 tc_num;
339 	u8 vlan_fliter_cap;
340 	u16 tqp_desc_num;
341 	u16 rx_buf_len;
342 	u16 vf_rss_size_max;
343 	u16 pf_rss_size_max;
344 	u8 phy_addr;
345 	u8 media_type;
346 	u8 mac_addr[ETH_ALEN];
347 	u8 default_speed;
348 	u32 numa_node_map;
349 	u32 tx_spare_buf_size;
350 	u16 speed_ability;
351 	u16 umv_space;
352 };
353 
354 struct hclge_tm_info {
355 	u8 num_tc;
356 	u8 num_pg;      /* It must be 1 if vNET-Base schd */
357 	u8 pg_dwrr[HCLGE_PG_NUM];
358 	u8 prio_tc[HNAE3_MAX_USER_PRIO];
359 	struct hclge_pg_info pg_info[HCLGE_PG_NUM];
360 	struct hclge_tc_info tc_info[HNAE3_MAX_TC];
361 	enum hclge_fc_mode fc_mode;
362 	u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
363 	u8 pfc_en;	/* PFC enabled or not for user priority */
364 };
365 
366 /* max number of mac statistics on each version */
367 #define HCLGE_MAC_STATS_MAX_NUM_V1		87
368 #define HCLGE_MAC_STATS_MAX_NUM_V2		105
369 
370 struct hclge_comm_stats_str {
371 	char desc[ETH_GSTRING_LEN];
372 	u32 stats_num;
373 	unsigned long offset;
374 };
375 
376 /* mac stats ,opcode id: 0x0032 */
377 struct hclge_mac_stats {
378 	u64 mac_tx_mac_pause_num;
379 	u64 mac_rx_mac_pause_num;
380 	u64 rsv0;
381 	u64 mac_tx_pfc_pri0_pkt_num;
382 	u64 mac_tx_pfc_pri1_pkt_num;
383 	u64 mac_tx_pfc_pri2_pkt_num;
384 	u64 mac_tx_pfc_pri3_pkt_num;
385 	u64 mac_tx_pfc_pri4_pkt_num;
386 	u64 mac_tx_pfc_pri5_pkt_num;
387 	u64 mac_tx_pfc_pri6_pkt_num;
388 	u64 mac_tx_pfc_pri7_pkt_num;
389 	u64 mac_rx_pfc_pri0_pkt_num;
390 	u64 mac_rx_pfc_pri1_pkt_num;
391 	u64 mac_rx_pfc_pri2_pkt_num;
392 	u64 mac_rx_pfc_pri3_pkt_num;
393 	u64 mac_rx_pfc_pri4_pkt_num;
394 	u64 mac_rx_pfc_pri5_pkt_num;
395 	u64 mac_rx_pfc_pri6_pkt_num;
396 	u64 mac_rx_pfc_pri7_pkt_num;
397 	u64 mac_tx_total_pkt_num;
398 	u64 mac_tx_total_oct_num;
399 	u64 mac_tx_good_pkt_num;
400 	u64 mac_tx_bad_pkt_num;
401 	u64 mac_tx_good_oct_num;
402 	u64 mac_tx_bad_oct_num;
403 	u64 mac_tx_uni_pkt_num;
404 	u64 mac_tx_multi_pkt_num;
405 	u64 mac_tx_broad_pkt_num;
406 	u64 mac_tx_undersize_pkt_num;
407 	u64 mac_tx_oversize_pkt_num;
408 	u64 mac_tx_64_oct_pkt_num;
409 	u64 mac_tx_65_127_oct_pkt_num;
410 	u64 mac_tx_128_255_oct_pkt_num;
411 	u64 mac_tx_256_511_oct_pkt_num;
412 	u64 mac_tx_512_1023_oct_pkt_num;
413 	u64 mac_tx_1024_1518_oct_pkt_num;
414 	u64 mac_tx_1519_2047_oct_pkt_num;
415 	u64 mac_tx_2048_4095_oct_pkt_num;
416 	u64 mac_tx_4096_8191_oct_pkt_num;
417 	u64 rsv1;
418 	u64 mac_tx_8192_9216_oct_pkt_num;
419 	u64 mac_tx_9217_12287_oct_pkt_num;
420 	u64 mac_tx_12288_16383_oct_pkt_num;
421 	u64 mac_tx_1519_max_good_oct_pkt_num;
422 	u64 mac_tx_1519_max_bad_oct_pkt_num;
423 
424 	u64 mac_rx_total_pkt_num;
425 	u64 mac_rx_total_oct_num;
426 	u64 mac_rx_good_pkt_num;
427 	u64 mac_rx_bad_pkt_num;
428 	u64 mac_rx_good_oct_num;
429 	u64 mac_rx_bad_oct_num;
430 	u64 mac_rx_uni_pkt_num;
431 	u64 mac_rx_multi_pkt_num;
432 	u64 mac_rx_broad_pkt_num;
433 	u64 mac_rx_undersize_pkt_num;
434 	u64 mac_rx_oversize_pkt_num;
435 	u64 mac_rx_64_oct_pkt_num;
436 	u64 mac_rx_65_127_oct_pkt_num;
437 	u64 mac_rx_128_255_oct_pkt_num;
438 	u64 mac_rx_256_511_oct_pkt_num;
439 	u64 mac_rx_512_1023_oct_pkt_num;
440 	u64 mac_rx_1024_1518_oct_pkt_num;
441 	u64 mac_rx_1519_2047_oct_pkt_num;
442 	u64 mac_rx_2048_4095_oct_pkt_num;
443 	u64 mac_rx_4096_8191_oct_pkt_num;
444 	u64 rsv2;
445 	u64 mac_rx_8192_9216_oct_pkt_num;
446 	u64 mac_rx_9217_12287_oct_pkt_num;
447 	u64 mac_rx_12288_16383_oct_pkt_num;
448 	u64 mac_rx_1519_max_good_oct_pkt_num;
449 	u64 mac_rx_1519_max_bad_oct_pkt_num;
450 
451 	u64 mac_tx_fragment_pkt_num;
452 	u64 mac_tx_undermin_pkt_num;
453 	u64 mac_tx_jabber_pkt_num;
454 	u64 mac_tx_err_all_pkt_num;
455 	u64 mac_tx_from_app_good_pkt_num;
456 	u64 mac_tx_from_app_bad_pkt_num;
457 	u64 mac_rx_fragment_pkt_num;
458 	u64 mac_rx_undermin_pkt_num;
459 	u64 mac_rx_jabber_pkt_num;
460 	u64 mac_rx_fcs_err_pkt_num;
461 	u64 mac_rx_send_app_good_pkt_num;
462 	u64 mac_rx_send_app_bad_pkt_num;
463 	u64 mac_tx_pfc_pause_pkt_num;
464 	u64 mac_rx_pfc_pause_pkt_num;
465 	u64 mac_tx_ctrl_pkt_num;
466 	u64 mac_rx_ctrl_pkt_num;
467 
468 	/* duration of pfc */
469 	u64 mac_tx_pfc_pri0_xoff_time;
470 	u64 mac_tx_pfc_pri1_xoff_time;
471 	u64 mac_tx_pfc_pri2_xoff_time;
472 	u64 mac_tx_pfc_pri3_xoff_time;
473 	u64 mac_tx_pfc_pri4_xoff_time;
474 	u64 mac_tx_pfc_pri5_xoff_time;
475 	u64 mac_tx_pfc_pri6_xoff_time;
476 	u64 mac_tx_pfc_pri7_xoff_time;
477 	u64 mac_rx_pfc_pri0_xoff_time;
478 	u64 mac_rx_pfc_pri1_xoff_time;
479 	u64 mac_rx_pfc_pri2_xoff_time;
480 	u64 mac_rx_pfc_pri3_xoff_time;
481 	u64 mac_rx_pfc_pri4_xoff_time;
482 	u64 mac_rx_pfc_pri5_xoff_time;
483 	u64 mac_rx_pfc_pri6_xoff_time;
484 	u64 mac_rx_pfc_pri7_xoff_time;
485 
486 	/* duration of pause */
487 	u64 mac_tx_pause_xoff_time;
488 	u64 mac_rx_pause_xoff_time;
489 };
490 
491 #define HCLGE_STATS_TIMER_INTERVAL	300UL
492 
493 /* fec stats ,opcode id: 0x0316 */
494 #define HCLGE_FEC_STATS_MAX_LANES	8
495 struct hclge_fec_stats {
496 	/* fec rs mode total stats */
497 	u64 rs_corr_blocks;
498 	u64 rs_uncorr_blocks;
499 	u64 rs_error_blocks;
500 	/* fec base-r mode per lanes stats */
501 	u64 base_r_lane_num;
502 	u64 base_r_corr_blocks;
503 	u64 base_r_uncorr_blocks;
504 	union {
505 		struct {
506 			u64 base_r_corr_per_lanes[HCLGE_FEC_STATS_MAX_LANES];
507 			u64 base_r_uncorr_per_lanes[HCLGE_FEC_STATS_MAX_LANES];
508 		};
509 		u64 per_lanes[HCLGE_FEC_STATS_MAX_LANES * 2];
510 	};
511 };
512 
513 struct hclge_vlan_type_cfg {
514 	u16 rx_ot_fst_vlan_type;
515 	u16 rx_ot_sec_vlan_type;
516 	u16 rx_in_fst_vlan_type;
517 	u16 rx_in_sec_vlan_type;
518 	u16 tx_ot_vlan_type;
519 	u16 tx_in_vlan_type;
520 };
521 
522 enum HCLGE_FD_MODE {
523 	HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1,
524 	HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2,
525 	HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1,
526 	HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2,
527 };
528 
529 enum HCLGE_FD_KEY_TYPE {
530 	HCLGE_FD_KEY_BASE_ON_PTYPE,
531 	HCLGE_FD_KEY_BASE_ON_TUPLE,
532 };
533 
534 enum HCLGE_FD_STAGE {
535 	HCLGE_FD_STAGE_1,
536 	HCLGE_FD_STAGE_2,
537 	MAX_STAGE_NUM,
538 };
539 
540 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet
541  * INNER_XXX indicate tuples in tunneled header of tunnel packet or
542  *           tuples of non-tunnel packet
543  */
544 enum HCLGE_FD_TUPLE {
545 	OUTER_DST_MAC,
546 	OUTER_SRC_MAC,
547 	OUTER_VLAN_TAG_FST,
548 	OUTER_VLAN_TAG_SEC,
549 	OUTER_ETH_TYPE,
550 	OUTER_L2_RSV,
551 	OUTER_IP_TOS,
552 	OUTER_IP_PROTO,
553 	OUTER_SRC_IP,
554 	OUTER_DST_IP,
555 	OUTER_L3_RSV,
556 	OUTER_SRC_PORT,
557 	OUTER_DST_PORT,
558 	OUTER_L4_RSV,
559 	OUTER_TUN_VNI,
560 	OUTER_TUN_FLOW_ID,
561 	INNER_DST_MAC,
562 	INNER_SRC_MAC,
563 	INNER_VLAN_TAG_FST,
564 	INNER_VLAN_TAG_SEC,
565 	INNER_ETH_TYPE,
566 	INNER_L2_RSV,
567 	INNER_IP_TOS,
568 	INNER_IP_PROTO,
569 	INNER_SRC_IP,
570 	INNER_DST_IP,
571 	INNER_L3_RSV,
572 	INNER_SRC_PORT,
573 	INNER_DST_PORT,
574 	INNER_L4_RSV,
575 	MAX_TUPLE,
576 };
577 
578 #define HCLGE_FD_TUPLE_USER_DEF_TUPLES \
579 	(BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV))
580 
581 enum HCLGE_FD_META_DATA {
582 	PACKET_TYPE_ID,
583 	IP_FRAGEMENT,
584 	ROCE_TYPE,
585 	NEXT_KEY,
586 	VLAN_NUMBER,
587 	SRC_VPORT,
588 	DST_VPORT,
589 	TUNNEL_PACKET,
590 	MAX_META_DATA,
591 };
592 
593 enum HCLGE_FD_KEY_OPT {
594 	KEY_OPT_U8,
595 	KEY_OPT_LE16,
596 	KEY_OPT_LE32,
597 	KEY_OPT_MAC,
598 	KEY_OPT_IP,
599 	KEY_OPT_VNI,
600 };
601 
602 struct key_info {
603 	u8 key_type;
604 	u8 key_length; /* use bit as unit */
605 	enum HCLGE_FD_KEY_OPT key_opt;
606 	int offset;
607 	int moffset;
608 };
609 
610 #define MAX_KEY_LENGTH	400
611 #define MAX_KEY_DWORDS	DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4)
612 #define MAX_KEY_BYTES	(MAX_KEY_DWORDS * 4)
613 #define MAX_META_DATA_LENGTH	32
614 
615 #define HCLGE_FD_MAX_USER_DEF_OFFSET	9000
616 #define HCLGE_FD_USER_DEF_DATA		GENMASK(15, 0)
617 #define HCLGE_FD_USER_DEF_OFFSET	GENMASK(15, 0)
618 #define HCLGE_FD_USER_DEF_OFFSET_UNMASK	GENMASK(15, 0)
619 
620 /* assigned by firmware, the real filter number for each pf may be less */
621 #define MAX_FD_FILTER_NUM	4096
622 #define HCLGE_ARFS_EXPIRE_INTERVAL	5UL
623 
624 #define hclge_read_dev(a, reg) \
625 	hclge_comm_read_reg((a)->hw.io_base, reg)
626 #define hclge_write_dev(a, reg, value) \
627 	hclge_comm_write_reg((a)->hw.io_base, reg, value)
628 
629 enum HCLGE_FD_ACTIVE_RULE_TYPE {
630 	HCLGE_FD_RULE_NONE,
631 	HCLGE_FD_ARFS_ACTIVE,
632 	HCLGE_FD_EP_ACTIVE,
633 	HCLGE_FD_TC_FLOWER_ACTIVE,
634 };
635 
636 enum HCLGE_FD_PACKET_TYPE {
637 	NIC_PACKET,
638 	ROCE_PACKET,
639 };
640 
641 enum HCLGE_FD_ACTION {
642 	HCLGE_FD_ACTION_SELECT_QUEUE,
643 	HCLGE_FD_ACTION_DROP_PACKET,
644 	HCLGE_FD_ACTION_SELECT_TC,
645 };
646 
647 enum HCLGE_FD_NODE_STATE {
648 	HCLGE_FD_TO_ADD,
649 	HCLGE_FD_TO_DEL,
650 	HCLGE_FD_ACTIVE,
651 	HCLGE_FD_DELETED,
652 };
653 
654 enum HCLGE_FD_USER_DEF_LAYER {
655 	HCLGE_FD_USER_DEF_NONE,
656 	HCLGE_FD_USER_DEF_L2,
657 	HCLGE_FD_USER_DEF_L3,
658 	HCLGE_FD_USER_DEF_L4,
659 };
660 
661 #define HCLGE_FD_USER_DEF_LAYER_NUM 3
662 struct hclge_fd_user_def_cfg {
663 	u16 ref_cnt;
664 	u16 offset;
665 };
666 
667 struct hclge_fd_user_def_info {
668 	enum HCLGE_FD_USER_DEF_LAYER layer;
669 	u16 data;
670 	u16 data_mask;
671 	u16 offset;
672 };
673 
674 struct hclge_fd_key_cfg {
675 	u8 key_sel;
676 	u8 inner_sipv6_word_en;
677 	u8 inner_dipv6_word_en;
678 	u8 outer_sipv6_word_en;
679 	u8 outer_dipv6_word_en;
680 	u32 tuple_active;
681 	u32 meta_data_active;
682 };
683 
684 struct hclge_fd_cfg {
685 	u8 fd_mode;
686 	u16 max_key_length; /* use bit as unit */
687 	u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */
688 	u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */
689 	struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM];
690 	struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM];
691 };
692 
693 #define IPV4_INDEX	3
694 #define IPV6_SIZE	4
695 struct hclge_fd_rule_tuples {
696 	u8 src_mac[ETH_ALEN];
697 	u8 dst_mac[ETH_ALEN];
698 	/* Be compatible for ip address of both ipv4 and ipv6.
699 	 * For ipv4 address, we store it in src/dst_ip[3].
700 	 */
701 	u32 src_ip[IPV6_SIZE];
702 	u32 dst_ip[IPV6_SIZE];
703 	u16 src_port;
704 	u16 dst_port;
705 	u16 vlan_tag1;
706 	u16 ether_proto;
707 	u16 l2_user_def;
708 	u16 l3_user_def;
709 	u32 l4_user_def;
710 	u8 ip_tos;
711 	u8 ip_proto;
712 };
713 
714 struct hclge_fd_rule {
715 	struct hlist_node rule_node;
716 	struct hclge_fd_rule_tuples tuples;
717 	struct hclge_fd_rule_tuples tuples_mask;
718 	u32 unused_tuple;
719 	u32 flow_type;
720 	union {
721 		struct {
722 			unsigned long cookie;
723 			u8 tc;
724 		} cls_flower;
725 		struct {
726 			u16 flow_id; /* only used for arfs */
727 		} arfs;
728 		struct {
729 			struct hclge_fd_user_def_info user_def;
730 		} ep;
731 	};
732 	u16 queue_id;
733 	u16 vf_id;
734 	u16 location;
735 	enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type;
736 	enum HCLGE_FD_NODE_STATE state;
737 	u8 action;
738 };
739 
740 struct hclge_fd_ad_data {
741 	u16 ad_id;
742 	u8 drop_packet;
743 	u8 forward_to_direct_queue;
744 	u16 queue_id;
745 	u8 use_counter;
746 	u8 counter_id;
747 	u8 use_next_stage;
748 	u8 write_rule_id_to_bd;
749 	u8 next_input_key;
750 	u16 rule_id;
751 	u16 tc_size;
752 	u8 override_tc;
753 };
754 
755 enum HCLGE_MAC_NODE_STATE {
756 	HCLGE_MAC_TO_ADD,
757 	HCLGE_MAC_TO_DEL,
758 	HCLGE_MAC_ACTIVE
759 };
760 
761 struct hclge_mac_node {
762 	struct list_head node;
763 	enum HCLGE_MAC_NODE_STATE state;
764 	u8 mac_addr[ETH_ALEN];
765 };
766 
767 enum HCLGE_MAC_ADDR_TYPE {
768 	HCLGE_MAC_ADDR_UC,
769 	HCLGE_MAC_ADDR_MC
770 };
771 
772 struct hclge_vport_vlan_cfg {
773 	struct list_head node;
774 	int hd_tbl_status;
775 	u16 vlan_id;
776 };
777 
778 struct hclge_rst_stats {
779 	u32 reset_done_cnt;	/* the number of reset has completed */
780 	u32 hw_reset_done_cnt;	/* the number of HW reset has completed */
781 	u32 pf_rst_cnt;		/* the number of PF reset */
782 	u32 flr_rst_cnt;	/* the number of FLR */
783 	u32 global_rst_cnt;	/* the number of GLOBAL */
784 	u32 imp_rst_cnt;	/* the number of IMP reset */
785 	u32 reset_cnt;		/* the number of reset */
786 	u32 reset_fail_cnt;	/* the number of reset fail */
787 };
788 
789 /* time and register status when mac tunnel interruption occur */
790 struct hclge_mac_tnl_stats {
791 	u64 time;
792 	u32 status;
793 };
794 
795 #define HCLGE_RESET_INTERVAL	(10 * HZ)
796 #define HCLGE_WAIT_RESET_DONE	100
797 
798 #pragma pack(1)
799 struct hclge_vf_vlan_cfg {
800 	u8 mbx_cmd;
801 	u8 subcode;
802 	union {
803 		struct {
804 			u8 is_kill;
805 			__le16 vlan;
806 			__le16 proto;
807 		};
808 		u8 enable;
809 	};
810 };
811 
812 #pragma pack()
813 
814 /* For each bit of TCAM entry, it uses a pair of 'x' and
815  * 'y' to indicate which value to match, like below:
816  * ----------------------------------
817  * | bit x | bit y |  search value  |
818  * ----------------------------------
819  * |   0   |   0   |   always hit   |
820  * ----------------------------------
821  * |   1   |   0   |   match '0'    |
822  * ----------------------------------
823  * |   0   |   1   |   match '1'    |
824  * ----------------------------------
825  * |   1   |   1   |   invalid      |
826  * ----------------------------------
827  * Then for input key(k) and mask(v), we can calculate the value by
828  * the formulae:
829  *	x = (~k) & v
830  *	y = (k ^ ~v) & k
831  */
832 #define calc_x(x, k, v) (x = ~(k) & (v))
833 #define calc_y(y, k, v) \
834 	do { \
835 		const typeof(k) _k_ = (k); \
836 		const typeof(v) _v_ = (v); \
837 		(y) = (_k_ ^ ~_v_) & (_k_); \
838 	} while (0)
839 
840 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
841 #define HCLGE_STATS_READ(p, offset) (*(u64 *)((u8 *)(p) + (offset)))
842 
843 #define HCLGE_MAC_TNL_LOG_SIZE	8
844 #define HCLGE_VPORT_NUM 256
845 struct hclge_dev {
846 	struct pci_dev *pdev;
847 	struct hnae3_ae_dev *ae_dev;
848 	struct hclge_hw hw;
849 	struct hclge_misc_vector misc_vector;
850 	struct hclge_mac_stats mac_stats;
851 	struct hclge_fec_stats fec_stats;
852 	unsigned long state;
853 	unsigned long flr_state;
854 	unsigned long last_reset_time;
855 
856 	enum hnae3_reset_type reset_type;
857 	enum hnae3_reset_type reset_level;
858 	unsigned long default_reset_request;
859 	unsigned long reset_request;	/* reset has been requested */
860 	unsigned long reset_pending;	/* client rst is pending to be served */
861 	struct hclge_rst_stats rst_stats;
862 	struct semaphore reset_sem;	/* protect reset process */
863 	u32 fw_version;
864 	u16 num_tqps;			/* Num task queue pairs of this PF */
865 	u16 num_req_vfs;		/* Num VFs requested for this PF */
866 
867 	u16 base_tqp_pid;	/* Base task tqp physical id of this PF */
868 	u16 alloc_rss_size;		/* Allocated RSS task queue */
869 	u16 vf_rss_size_max;		/* HW defined VF max RSS task queue */
870 	u16 pf_rss_size_max;		/* HW defined PF max RSS task queue */
871 	u32 tx_spare_buf_size;		/* HW defined TX spare buffer size */
872 
873 	u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */
874 	u16 num_alloc_vport;		/* Num vports this driver supports */
875 	u32 numa_node_mask;
876 	u16 rx_buf_len;
877 	u16 num_tx_desc;		/* desc num of per tx queue */
878 	u16 num_rx_desc;		/* desc num of per rx queue */
879 	u8 hw_tc_map;
880 	enum hclge_fc_mode fc_mode_last_time;
881 	u8 support_sfp_query;
882 
883 #define HCLGE_FLAG_TC_BASE_SCH_MODE		1
884 #define HCLGE_FLAG_VNET_BASE_SCH_MODE		2
885 	u8 tx_sch_mode;
886 	u8 tc_max;
887 	u8 pfc_max;
888 
889 	u8 default_up;
890 	u8 dcbx_cap;
891 	struct hclge_tm_info tm_info;
892 
893 	u16 num_msi;
894 	u16 num_msi_left;
895 	u16 num_msi_used;
896 	u16 *vector_status;
897 	int *vector_irq;
898 	u16 num_nic_msi;	/* Num of nic vectors for this PF */
899 	u16 num_roce_msi;	/* Num of roce vectors for this PF */
900 
901 	unsigned long service_timer_period;
902 	unsigned long service_timer_previous;
903 	struct timer_list reset_timer;
904 	struct delayed_work service_task;
905 
906 	bool cur_promisc;
907 	int num_alloc_vfs;	/* Actual number of VFs allocated */
908 
909 	struct hclge_comm_tqp *htqp;
910 	struct hclge_vport *vport;
911 
912 	struct dentry *hclge_dbgfs;
913 
914 	struct hnae3_client *nic_client;
915 	struct hnae3_client *roce_client;
916 
917 #define HCLGE_FLAG_MAIN			BIT(0)
918 #define HCLGE_FLAG_DCB_CAPABLE		BIT(1)
919 #define HCLGE_FLAG_DCB_ENABLE		BIT(2)
920 #define HCLGE_FLAG_MQPRIO_ENABLE	BIT(3)
921 	u32 flag;
922 
923 	u32 pkt_buf_size; /* Total pf buf size for tx/rx */
924 	u32 tx_buf_size; /* Tx buffer size for each TC */
925 	u32 dv_buf_size; /* Dv buffer size for each TC */
926 
927 	u32 mps; /* Max packet size */
928 	/* vport_lock protect resource shared by vports */
929 	struct mutex vport_lock;
930 
931 	struct hclge_vlan_type_cfg vlan_type_cfg;
932 
933 	unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)];
934 	unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
935 
936 	unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
937 
938 	struct hclge_fd_cfg fd_cfg;
939 	struct hlist_head fd_rule_list;
940 	spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */
941 	u16 hclge_fd_rule_num;
942 	unsigned long serv_processed_cnt;
943 	unsigned long last_serv_processed;
944 	unsigned long last_rst_scheduled;
945 	unsigned long last_mbx_scheduled;
946 	unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)];
947 	enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type;
948 	u8 fd_en;
949 	bool gro_en;
950 
951 	u16 wanted_umv_size;
952 	/* max available unicast mac vlan space */
953 	u16 max_umv_size;
954 	/* private unicast mac vlan space, it's same for PF and its VFs */
955 	u16 priv_umv_size;
956 	/* unicast mac vlan space shared by PF and its VFs */
957 	u16 share_umv_size;
958 	/* multicast mac address number used by PF and its VFs */
959 	u16 used_mc_mac_num;
960 
961 	DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats,
962 		      HCLGE_MAC_TNL_LOG_SIZE);
963 
964 	struct hclge_ptp *ptp;
965 	struct devlink *devlink;
966 	struct hclge_comm_rss_cfg rss_cfg;
967 };
968 
969 /* VPort level vlan tag configuration for TX direction */
970 struct hclge_tx_vtag_cfg {
971 	bool accept_tag1;	/* Whether accept tag1 packet from host */
972 	bool accept_untag1;	/* Whether accept untag1 packet from host */
973 	bool accept_tag2;
974 	bool accept_untag2;
975 	bool insert_tag1_en;	/* Whether insert inner vlan tag */
976 	bool insert_tag2_en;	/* Whether insert outer vlan tag */
977 	u16  default_tag1;	/* The default inner vlan tag to insert */
978 	u16  default_tag2;	/* The default outer vlan tag to insert */
979 	bool tag_shift_mode_en;
980 };
981 
982 /* VPort level vlan tag configuration for RX direction */
983 struct hclge_rx_vtag_cfg {
984 	bool rx_vlan_offload_en; /* Whether enable rx vlan offload */
985 	bool strip_tag1_en;	 /* Whether strip inner vlan tag */
986 	bool strip_tag2_en;	 /* Whether strip outer vlan tag */
987 	bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */
988 	bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */
989 	bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */
990 	bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */
991 };
992 
993 enum HCLGE_VPORT_STATE {
994 	HCLGE_VPORT_STATE_ALIVE,
995 	HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
996 	HCLGE_VPORT_STATE_PROMISC_CHANGE,
997 	HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
998 	HCLGE_VPORT_STATE_INITED,
999 	HCLGE_VPORT_STATE_MAX
1000 };
1001 
1002 enum HCLGE_VPORT_NEED_NOTIFY {
1003 	HCLGE_VPORT_NEED_NOTIFY_RESET,
1004 	HCLGE_VPORT_NEED_NOTIFY_VF_VLAN,
1005 };
1006 
1007 struct hclge_vlan_info {
1008 	u16 vlan_proto; /* so far support 802.1Q only */
1009 	u16 qos;
1010 	u16 vlan_tag;
1011 };
1012 
1013 struct hclge_port_base_vlan_config {
1014 	u16 state;
1015 	bool tbl_sta;
1016 	struct hclge_vlan_info vlan_info;
1017 	struct hclge_vlan_info old_vlan_info;
1018 };
1019 
1020 struct hclge_vf_info {
1021 	int link_state;
1022 	u8 mac[ETH_ALEN];
1023 	u32 spoofchk;
1024 	u32 max_tx_rate;
1025 	u32 trusted;
1026 	u8 request_uc_en;
1027 	u8 request_mc_en;
1028 	u8 request_bc_en;
1029 };
1030 
1031 struct hclge_vport {
1032 	u16 alloc_tqps;	/* Allocated Tx/Rx queues */
1033 
1034 	u16 qs_offset;
1035 	u32 bw_limit;		/* VSI BW Limit (0 = disabled) */
1036 	u8  dwrr;
1037 
1038 	bool req_vlan_fltr_en;
1039 	bool cur_vlan_fltr_en;
1040 	unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
1041 	struct hclge_port_base_vlan_config port_base_vlan_cfg;
1042 	struct hclge_tx_vtag_cfg  txvlan_cfg;
1043 	struct hclge_rx_vtag_cfg  rxvlan_cfg;
1044 
1045 	u16 used_umv_num;
1046 
1047 	u16 vport_id;
1048 	struct hclge_dev *back;  /* Back reference to associated dev */
1049 	struct hnae3_handle nic;
1050 	struct hnae3_handle roce;
1051 
1052 	unsigned long state;
1053 	unsigned long need_notify;
1054 	unsigned long last_active_jiffies;
1055 	u32 mps; /* Max packet size */
1056 	struct hclge_vf_info vf_info;
1057 
1058 	u8 overflow_promisc_flags;
1059 	u8 last_promisc_flags;
1060 
1061 	spinlock_t mac_list_lock; /* protect mac address need to add/detele */
1062 	struct list_head uc_mac_list;   /* Store VF unicast table */
1063 	struct list_head mc_mac_list;   /* Store VF multicast table */
1064 
1065 	struct list_head vlan_list;     /* Store VF vlan table */
1066 };
1067 
1068 struct hclge_speed_bit_map {
1069 	u32 speed;
1070 	u32 speed_bit;
1071 };
1072 
1073 struct hclge_mac_speed_map {
1074 	u32 speed_drv; /* speed defined in driver */
1075 	u32 speed_fw; /* speed defined in firmware */
1076 };
1077 
1078 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
1079 				 bool en_mc_pmc, bool en_bc_pmc);
1080 int hclge_add_uc_addr_common(struct hclge_vport *vport,
1081 			     const unsigned char *addr);
1082 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
1083 			    const unsigned char *addr);
1084 int hclge_add_mc_addr_common(struct hclge_vport *vport,
1085 			     const unsigned char *addr);
1086 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
1087 			    const unsigned char *addr);
1088 
1089 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
1090 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
1091 				int vector_id, bool en,
1092 				struct hnae3_ring_chain_node *ring_chain);
1093 
hclge_get_queue_id(struct hnae3_queue * queue)1094 static inline int hclge_get_queue_id(struct hnae3_queue *queue)
1095 {
1096 	struct hclge_comm_tqp *tqp =
1097 			container_of(queue, struct hclge_comm_tqp, q);
1098 
1099 	return tqp->index;
1100 }
1101 
1102 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport);
1103 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num);
1104 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
1105 			  u16 vlan_id, bool is_kill);
1106 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable);
1107 
1108 int hclge_buffer_alloc(struct hclge_dev *hdev);
1109 int hclge_rss_init_hw(struct hclge_dev *hdev);
1110 
1111 void hclge_mbx_handler(struct hclge_dev *hdev);
1112 int hclge_reset_tqp(struct hnae3_handle *handle);
1113 int hclge_cfg_flowctrl(struct hclge_dev *hdev);
1114 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id);
1115 int hclge_vport_start(struct hclge_vport *vport);
1116 void hclge_vport_stop(struct hclge_vport *vport);
1117 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu);
1118 int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,
1119 		       char *buf, int len);
1120 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id);
1121 int hclge_notify_client(struct hclge_dev *hdev,
1122 			enum hnae3_reset_notify_type type);
1123 int hclge_update_mac_list(struct hclge_vport *vport,
1124 			  enum HCLGE_MAC_NODE_STATE state,
1125 			  enum HCLGE_MAC_ADDR_TYPE mac_type,
1126 			  const unsigned char *addr);
1127 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport,
1128 				       const u8 *old_addr, const u8 *new_addr);
1129 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,
1130 				  enum HCLGE_MAC_ADDR_TYPE mac_type);
1131 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list);
1132 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev);
1133 void hclge_restore_mac_table_common(struct hclge_vport *vport);
1134 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev);
1135 void hclge_restore_vport_vlan_table(struct hclge_vport *vport);
1136 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
1137 				    struct hclge_vlan_info *vlan_info);
1138 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid,
1139 				      u16 state,
1140 				      struct hclge_vlan_info *vlan_info);
1141 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time);
1142 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev,
1143 				struct hclge_desc *desc);
1144 void hclge_report_hw_error(struct hclge_dev *hdev,
1145 			   enum hnae3_hw_error_type type);
1146 void hclge_inform_vf_promisc_info(struct hclge_vport *vport);
1147 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len);
1148 int hclge_push_vf_link_status(struct hclge_vport *vport);
1149 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en);
1150 int hclge_mac_update_stats(struct hclge_dev *hdev);
1151 #endif
1152