1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPMC support functions
4 *
5 * Copyright (C) 2005-2006 Nokia Corporation
6 *
7 * Author: Juha Yrjola
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 */
12 #include <linux/cpu_pm.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
19 #include <linux/ioport.h>
20 #include <linux/spinlock.h>
21 #include <linux/io.h>
22 #include <linux/gpio/driver.h>
23 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
24 #include <linux/gpio/machine.h>
25 #include <linux/interrupt.h>
26 #include <linux/irqdomain.h>
27 #include <linux/platform_device.h>
28 #include <linux/of.h>
29 #include <linux/of_address.h>
30 #include <linux/of_device.h>
31 #include <linux/of_platform.h>
32 #include <linux/omap-gpmc.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/sizes.h>
35
36 #include <linux/platform_data/mtd-nand-omap2.h>
37
38 #define DEVICE_NAME "omap-gpmc"
39
40 /* GPMC register offsets */
41 #define GPMC_REVISION 0x00
42 #define GPMC_SYSCONFIG 0x10
43 #define GPMC_SYSSTATUS 0x14
44 #define GPMC_IRQSTATUS 0x18
45 #define GPMC_IRQENABLE 0x1c
46 #define GPMC_TIMEOUT_CONTROL 0x40
47 #define GPMC_ERR_ADDRESS 0x44
48 #define GPMC_ERR_TYPE 0x48
49 #define GPMC_CONFIG 0x50
50 #define GPMC_STATUS 0x54
51 #define GPMC_PREFETCH_CONFIG1 0x1e0
52 #define GPMC_PREFETCH_CONFIG2 0x1e4
53 #define GPMC_PREFETCH_CONTROL 0x1ec
54 #define GPMC_PREFETCH_STATUS 0x1f0
55 #define GPMC_ECC_CONFIG 0x1f4
56 #define GPMC_ECC_CONTROL 0x1f8
57 #define GPMC_ECC_SIZE_CONFIG 0x1fc
58 #define GPMC_ECC1_RESULT 0x200
59 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
60 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
61 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
62 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
63 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
64 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
65 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
66
67 /* GPMC ECC control settings */
68 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
69 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
70 #define GPMC_ECC_CTRL_ECCREG1 0x001
71 #define GPMC_ECC_CTRL_ECCREG2 0x002
72 #define GPMC_ECC_CTRL_ECCREG3 0x003
73 #define GPMC_ECC_CTRL_ECCREG4 0x004
74 #define GPMC_ECC_CTRL_ECCREG5 0x005
75 #define GPMC_ECC_CTRL_ECCREG6 0x006
76 #define GPMC_ECC_CTRL_ECCREG7 0x007
77 #define GPMC_ECC_CTRL_ECCREG8 0x008
78 #define GPMC_ECC_CTRL_ECCREG9 0x009
79
80 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
81
82 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
83
84 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
85 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
86 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
87 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
88 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
89 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
90
91 #define GPMC_CS0_OFFSET 0x60
92 #define GPMC_CS_SIZE 0x30
93 #define GPMC_BCH_SIZE 0x10
94
95 /*
96 * The first 1MB of GPMC address space is typically mapped to
97 * the internal ROM. Never allocate the first page, to
98 * facilitate bug detection; even if we didn't boot from ROM.
99 * As GPMC minimum partition size is 16MB we can only start from
100 * there.
101 */
102 #define GPMC_MEM_START 0x1000000
103 #define GPMC_MEM_END 0x3FFFFFFF
104
105 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
106 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
107
108 #define CS_NUM_SHIFT 24
109 #define ENABLE_PREFETCH (0x1 << 7)
110 #define DMA_MPU_MODE 2
111
112 #define GPMC_REVISION_MAJOR(l) (((l) >> 4) & 0xf)
113 #define GPMC_REVISION_MINOR(l) ((l) & 0xf)
114
115 #define GPMC_HAS_WR_ACCESS 0x1
116 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
117 #define GPMC_HAS_MUX_AAD 0x4
118
119 #define GPMC_NR_WAITPINS 4
120
121 #define GPMC_CS_CONFIG1 0x00
122 #define GPMC_CS_CONFIG2 0x04
123 #define GPMC_CS_CONFIG3 0x08
124 #define GPMC_CS_CONFIG4 0x0c
125 #define GPMC_CS_CONFIG5 0x10
126 #define GPMC_CS_CONFIG6 0x14
127 #define GPMC_CS_CONFIG7 0x18
128 #define GPMC_CS_NAND_COMMAND 0x1c
129 #define GPMC_CS_NAND_ADDRESS 0x20
130 #define GPMC_CS_NAND_DATA 0x24
131
132 /* Control Commands */
133 #define GPMC_CONFIG_RDY_BSY 0x00000001
134 #define GPMC_CONFIG_DEV_SIZE 0x00000002
135 #define GPMC_CONFIG_DEV_TYPE 0x00000003
136
137 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
138 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
139 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
140 #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
141 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
142 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
143 #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
144 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
145 /** CLKACTIVATIONTIME Max Ticks */
146 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
147 #define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
148 /** ATTACHEDDEVICEPAGELENGTH Max Value */
149 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
150 #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
151 #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
152 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
153 /** WAITMONITORINGTIME Max Ticks */
154 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
155 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
156 #define GPMC_CONFIG1_DEVICESIZE(val) (((val) & 3) << 12)
157 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
158 /** DEVICESIZE Max Value */
159 #define GPMC_CONFIG1_DEVICESIZE_MAX 1
160 #define GPMC_CONFIG1_DEVICETYPE(val) (((val) & 3) << 10)
161 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
162 #define GPMC_CONFIG1_MUXTYPE(val) (((val) & 3) << 8)
163 #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
164 #define GPMC_CONFIG1_FCLK_DIV(val) ((val) & 3)
165 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
166 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
167 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
168 #define GPMC_CONFIG7_CSVALID (1 << 6)
169
170 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
171 #define GPMC_CONFIG7_CSVALID_MASK BIT(6)
172 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
173 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
174 /* All CONFIG7 bits except reserved bits */
175 #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
176 GPMC_CONFIG7_CSVALID_MASK | \
177 GPMC_CONFIG7_MASKADDRESS_MASK)
178
179 #define GPMC_DEVICETYPE_NOR 0
180 #define GPMC_DEVICETYPE_NAND 2
181 #define GPMC_CONFIG_WRITEPROTECT 0x00000010
182 #define WR_RD_PIN_MONITORING 0x00600000
183
184 /* ECC commands */
185 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
186 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
187 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
188
189 #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
190
191 enum gpmc_clk_domain {
192 GPMC_CD_FCLK,
193 GPMC_CD_CLK
194 };
195
196 struct gpmc_cs_data {
197 const char *name;
198
199 #define GPMC_CS_RESERVED (1 << 0)
200 u32 flags;
201
202 struct resource mem;
203 };
204
205 /* Structure to save gpmc cs context */
206 struct gpmc_cs_config {
207 u32 config1;
208 u32 config2;
209 u32 config3;
210 u32 config4;
211 u32 config5;
212 u32 config6;
213 u32 config7;
214 int is_valid;
215 };
216
217 /*
218 * Structure to save/restore gpmc context
219 * to support core off on OMAP3
220 */
221 struct omap3_gpmc_regs {
222 u32 sysconfig;
223 u32 irqenable;
224 u32 timeout_ctrl;
225 u32 config;
226 u32 prefetch_config1;
227 u32 prefetch_config2;
228 u32 prefetch_control;
229 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
230 };
231
232 struct gpmc_device {
233 struct device *dev;
234 int irq;
235 struct irq_chip irq_chip;
236 struct gpio_chip gpio_chip;
237 struct notifier_block nb;
238 struct omap3_gpmc_regs context;
239 int nirqs;
240 unsigned int is_suspended:1;
241 struct resource *data;
242 };
243
244 static struct irq_domain *gpmc_irq_domain;
245
246 static struct resource gpmc_mem_root;
247 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
248 static DEFINE_SPINLOCK(gpmc_mem_lock);
249 /* Define chip-selects as reserved by default until probe completes */
250 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
251 static unsigned int gpmc_nr_waitpins;
252 static unsigned int gpmc_capability;
253 static void __iomem *gpmc_base;
254
255 static struct clk *gpmc_l3_clk;
256
257 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
258
gpmc_write_reg(int idx,u32 val)259 static void gpmc_write_reg(int idx, u32 val)
260 {
261 writel_relaxed(val, gpmc_base + idx);
262 }
263
gpmc_read_reg(int idx)264 static u32 gpmc_read_reg(int idx)
265 {
266 return readl_relaxed(gpmc_base + idx);
267 }
268
gpmc_cs_write_reg(int cs,int idx,u32 val)269 void gpmc_cs_write_reg(int cs, int idx, u32 val)
270 {
271 void __iomem *reg_addr;
272
273 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
274 writel_relaxed(val, reg_addr);
275 }
276
gpmc_cs_read_reg(int cs,int idx)277 static u32 gpmc_cs_read_reg(int cs, int idx)
278 {
279 void __iomem *reg_addr;
280
281 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
282 return readl_relaxed(reg_addr);
283 }
284
285 /* TODO: Add support for gpmc_fck to clock framework and use it */
gpmc_get_fclk_period(void)286 static unsigned long gpmc_get_fclk_period(void)
287 {
288 unsigned long rate = clk_get_rate(gpmc_l3_clk);
289
290 rate /= 1000;
291 rate = 1000000000 / rate; /* In picoseconds */
292
293 return rate;
294 }
295
296 /**
297 * gpmc_get_clk_period - get period of selected clock domain in ps
298 * @cs: Chip Select Region.
299 * @cd: Clock Domain.
300 *
301 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
302 * prior to calling this function with GPMC_CD_CLK.
303 */
gpmc_get_clk_period(int cs,enum gpmc_clk_domain cd)304 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
305 {
306 unsigned long tick_ps = gpmc_get_fclk_period();
307 u32 l;
308 int div;
309
310 switch (cd) {
311 case GPMC_CD_CLK:
312 /* get current clk divider */
313 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
314 div = (l & 0x03) + 1;
315 /* get GPMC_CLK period */
316 tick_ps *= div;
317 break;
318 case GPMC_CD_FCLK:
319 default:
320 break;
321 }
322
323 return tick_ps;
324 }
325
gpmc_ns_to_clk_ticks(unsigned int time_ns,int cs,enum gpmc_clk_domain cd)326 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
327 enum gpmc_clk_domain cd)
328 {
329 unsigned long tick_ps;
330
331 /* Calculate in picosecs to yield more exact results */
332 tick_ps = gpmc_get_clk_period(cs, cd);
333
334 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
335 }
336
gpmc_ns_to_ticks(unsigned int time_ns)337 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
338 {
339 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
340 }
341
gpmc_ps_to_ticks(unsigned int time_ps)342 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
343 {
344 unsigned long tick_ps;
345
346 /* Calculate in picosecs to yield more exact results */
347 tick_ps = gpmc_get_fclk_period();
348
349 return (time_ps + tick_ps - 1) / tick_ps;
350 }
351
gpmc_clk_ticks_to_ns(unsigned int ticks,int cs,enum gpmc_clk_domain cd)352 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
353 enum gpmc_clk_domain cd)
354 {
355 return ticks * gpmc_get_clk_period(cs, cd) / 1000;
356 }
357
gpmc_ticks_to_ns(unsigned int ticks)358 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
359 {
360 return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
361 }
362
gpmc_ticks_to_ps(unsigned int ticks)363 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
364 {
365 return ticks * gpmc_get_fclk_period();
366 }
367
gpmc_round_ps_to_ticks(unsigned int time_ps)368 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
369 {
370 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
371
372 return ticks * gpmc_get_fclk_period();
373 }
374
gpmc_cs_modify_reg(int cs,int reg,u32 mask,bool value)375 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
376 {
377 u32 l;
378
379 l = gpmc_cs_read_reg(cs, reg);
380 if (value)
381 l |= mask;
382 else
383 l &= ~mask;
384 gpmc_cs_write_reg(cs, reg, l);
385 }
386
gpmc_cs_bool_timings(int cs,const struct gpmc_bool_timings * p)387 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
388 {
389 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
390 GPMC_CONFIG1_TIME_PARA_GRAN,
391 p->time_para_granularity);
392 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
393 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
394 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
395 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
396 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
397 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
398 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
399 GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
400 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
401 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
402 p->cycle2cyclesamecsen);
403 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
404 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
405 p->cycle2cyclediffcsen);
406 }
407
408 #ifdef CONFIG_OMAP_GPMC_DEBUG
409 /**
410 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
411 * @cs: Chip Select Region
412 * @reg: GPMC_CS_CONFIGn register offset.
413 * @st_bit: Start Bit
414 * @end_bit: End Bit. Must be >= @st_bit.
415 * @max: Maximum parameter value (before optional @shift).
416 * If 0, maximum is as high as @st_bit and @end_bit allow.
417 * @name: DTS node name, w/o "gpmc,"
418 * @cd: Clock Domain of timing parameter.
419 * @shift: Parameter value left shifts @shift, which is then printed instead of value.
420 * @raw: Raw Format Option.
421 * raw format: gpmc,name = <value>
422 * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/
423 * Where x ns -- y ns result in the same tick value.
424 * When @max is exceeded, "invalid" is printed inside comment.
425 * @noval: Parameter values equal to 0 are not printed.
426 * @return: Specified timing parameter (after optional @shift).
427 *
428 */
get_gpmc_timing_reg(int cs,int reg,int st_bit,int end_bit,int max,const char * name,const enum gpmc_clk_domain cd,int shift,bool raw,bool noval)429 static int get_gpmc_timing_reg(
430 /* timing specifiers */
431 int cs, int reg, int st_bit, int end_bit, int max,
432 const char *name, const enum gpmc_clk_domain cd,
433 /* value transform */
434 int shift,
435 /* format specifiers */
436 bool raw, bool noval)
437 {
438 u32 l;
439 int nr_bits;
440 int mask;
441 bool invalid;
442
443 l = gpmc_cs_read_reg(cs, reg);
444 nr_bits = end_bit - st_bit + 1;
445 mask = (1 << nr_bits) - 1;
446 l = (l >> st_bit) & mask;
447 if (!max)
448 max = mask;
449 invalid = l > max;
450 if (shift)
451 l = (shift << l);
452 if (noval && (l == 0))
453 return 0;
454 if (!raw) {
455 /* DTS tick format for timings in ns */
456 unsigned int time_ns;
457 unsigned int time_ns_min = 0;
458
459 if (l)
460 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
461 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
462 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
463 name, time_ns, time_ns_min, time_ns, l,
464 invalid ? "; invalid " : " ");
465 } else {
466 /* raw format */
467 pr_info("gpmc,%s = <%u>;%s\n", name, l,
468 invalid ? " /* invalid */" : "");
469 }
470
471 return l;
472 }
473
474 #define GPMC_PRINT_CONFIG(cs, config) \
475 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
476 gpmc_cs_read_reg(cs, config))
477 #define GPMC_GET_RAW(reg, st, end, field) \
478 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
479 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
480 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
481 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
482 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
483 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
484 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
485 #define GPMC_GET_TICKS(reg, st, end, field) \
486 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
487 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
488 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
489 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
490 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
491
gpmc_show_regs(int cs,const char * desc)492 static void gpmc_show_regs(int cs, const char *desc)
493 {
494 pr_info("gpmc cs%i %s:\n", cs, desc);
495 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
496 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
497 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
498 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
499 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
500 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
501 }
502
503 /*
504 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
505 * see commit c9fb809.
506 */
gpmc_cs_show_timings(int cs,const char * desc)507 static void gpmc_cs_show_timings(int cs, const char *desc)
508 {
509 gpmc_show_regs(cs, desc);
510
511 pr_info("gpmc cs%i access configuration:\n", cs);
512 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
513 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
514 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
515 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
516 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
517 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
518 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
519 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
520 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
521 "burst-length");
522 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
523 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
524 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
525 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
526 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
527
528 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
529
530 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
531
532 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
533 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
534
535 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
536 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
537
538 pr_info("gpmc cs%i timings configuration:\n", cs);
539 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
540 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
541 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
542
543 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
544 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
545 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
546 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
547 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
548 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
549 "adv-aad-mux-rd-off-ns");
550 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
551 "adv-aad-mux-wr-off-ns");
552 }
553
554 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
555 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
556 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
557 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns");
558 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
559 }
560 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
561 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
562
563 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
564 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
565 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
566
567 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
568
569 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
570 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
571
572 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
573 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
574 "wait-monitoring-ns", GPMC_CD_CLK);
575 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
576 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
577 "clk-activation-ns", GPMC_CD_FCLK);
578
579 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
580 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
581 }
582 #else
gpmc_cs_show_timings(int cs,const char * desc)583 static inline void gpmc_cs_show_timings(int cs, const char *desc)
584 {
585 }
586 #endif
587
588 /**
589 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
590 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
591 * prior to calling this function with @cd equal to GPMC_CD_CLK.
592 *
593 * @cs: Chip Select Region.
594 * @reg: GPMC_CS_CONFIGn register offset.
595 * @st_bit: Start Bit
596 * @end_bit: End Bit. Must be >= @st_bit.
597 * @max: Maximum parameter value.
598 * If 0, maximum is as high as @st_bit and @end_bit allow.
599 * @time: Timing parameter in ns.
600 * @cd: Timing parameter clock domain.
601 * @name: Timing parameter name.
602 * @return: 0 on success, -1 on error.
603 */
set_gpmc_timing_reg(int cs,int reg,int st_bit,int end_bit,int max,int time,enum gpmc_clk_domain cd,const char * name)604 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
605 int time, enum gpmc_clk_domain cd, const char *name)
606 {
607 u32 l;
608 int ticks, mask, nr_bits;
609
610 if (time == 0)
611 ticks = 0;
612 else
613 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
614 nr_bits = end_bit - st_bit + 1;
615 mask = (1 << nr_bits) - 1;
616
617 if (!max)
618 max = mask;
619
620 if (ticks > max) {
621 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
622 __func__, cs, name, time, ticks, max);
623
624 return -1;
625 }
626
627 l = gpmc_cs_read_reg(cs, reg);
628 #ifdef CONFIG_OMAP_GPMC_DEBUG
629 pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
630 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
631 (l >> st_bit) & mask, time);
632 #endif
633 l &= ~(mask << st_bit);
634 l |= ticks << st_bit;
635 gpmc_cs_write_reg(cs, reg, l);
636
637 return 0;
638 }
639
640 /**
641 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
642 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
643 * read --> don't sample bus too early
644 * write --> data is longer on bus
645 *
646 * Formula:
647 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
648 * / waitmonitoring_ticks)
649 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
650 * div <= 0 check.
651 *
652 * @wait_monitoring: WAITMONITORINGTIME in ns.
653 * @return: -1 on failure to scale, else proper divider > 0.
654 */
gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)655 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
656 {
657 int div = gpmc_ns_to_ticks(wait_monitoring);
658
659 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
660 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
661
662 if (div > 4)
663 return -1;
664 if (div <= 0)
665 div = 1;
666
667 return div;
668 }
669
670 /**
671 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
672 * @sync_clk: GPMC_CLK period in ps.
673 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
674 * Else, returns -1.
675 */
gpmc_calc_divider(unsigned int sync_clk)676 int gpmc_calc_divider(unsigned int sync_clk)
677 {
678 int div = gpmc_ps_to_ticks(sync_clk);
679
680 if (div > 4)
681 return -1;
682 if (div <= 0)
683 div = 1;
684
685 return div;
686 }
687
688 /**
689 * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
690 * @cs: Chip Select Region.
691 * @t: GPMC timing parameters.
692 * @s: GPMC timing settings.
693 * @return: 0 on success, -1 on error.
694 */
gpmc_cs_set_timings(int cs,const struct gpmc_timings * t,const struct gpmc_settings * s)695 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
696 const struct gpmc_settings *s)
697 {
698 int div, ret;
699 u32 l;
700
701 div = gpmc_calc_divider(t->sync_clk);
702 if (div < 0)
703 return -EINVAL;
704
705 /*
706 * See if we need to change the divider for waitmonitoringtime.
707 *
708 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
709 * pure asynchronous accesses, i.e. both read and write asynchronous.
710 * However, only do so if WAITMONITORINGTIME is actually used, i.e.
711 * either WAITREADMONITORING or WAITWRITEMONITORING is set.
712 *
713 * This statement must not change div to scale async WAITMONITORINGTIME
714 * to protect mixed synchronous and asynchronous accesses.
715 *
716 * We raise an error later if WAITMONITORINGTIME does not fit.
717 */
718 if (!s->sync_read && !s->sync_write &&
719 (s->wait_on_read || s->wait_on_write)
720 ) {
721 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
722 if (div < 0) {
723 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
724 __func__,
725 t->wait_monitoring
726 );
727 return -ENXIO;
728 }
729 }
730
731 ret = 0;
732 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on,
733 GPMC_CD_FCLK, "cs_on");
734 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off,
735 GPMC_CD_FCLK, "cs_rd_off");
736 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off,
737 GPMC_CD_FCLK, "cs_wr_off");
738 if (ret)
739 return -ENXIO;
740
741 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on,
742 GPMC_CD_FCLK, "adv_on");
743 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off,
744 GPMC_CD_FCLK, "adv_rd_off");
745 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off,
746 GPMC_CD_FCLK, "adv_wr_off");
747 if (ret)
748 return -ENXIO;
749
750 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
751 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0,
752 t->adv_aad_mux_on, GPMC_CD_FCLK,
753 "adv_aad_mux_on");
754 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0,
755 t->adv_aad_mux_rd_off, GPMC_CD_FCLK,
756 "adv_aad_mux_rd_off");
757 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0,
758 t->adv_aad_mux_wr_off, GPMC_CD_FCLK,
759 "adv_aad_mux_wr_off");
760 if (ret)
761 return -ENXIO;
762 }
763
764 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on,
765 GPMC_CD_FCLK, "oe_on");
766 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off,
767 GPMC_CD_FCLK, "oe_off");
768 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
769 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0,
770 t->oe_aad_mux_on, GPMC_CD_FCLK,
771 "oe_aad_mux_on");
772 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0,
773 t->oe_aad_mux_off, GPMC_CD_FCLK,
774 "oe_aad_mux_off");
775 }
776 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on,
777 GPMC_CD_FCLK, "we_on");
778 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off,
779 GPMC_CD_FCLK, "we_off");
780 if (ret)
781 return -ENXIO;
782
783 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle,
784 GPMC_CD_FCLK, "rd_cycle");
785 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle,
786 GPMC_CD_FCLK, "wr_cycle");
787 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access,
788 GPMC_CD_FCLK, "access");
789 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0,
790 t->page_burst_access, GPMC_CD_FCLK,
791 "page_burst_access");
792 if (ret)
793 return -ENXIO;
794
795 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0,
796 t->bus_turnaround, GPMC_CD_FCLK,
797 "bus_turnaround");
798 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0,
799 t->cycle2cycle_delay, GPMC_CD_FCLK,
800 "cycle2cycle_delay");
801 if (ret)
802 return -ENXIO;
803
804 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) {
805 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0,
806 t->wr_data_mux_bus, GPMC_CD_FCLK,
807 "wr_data_mux_bus");
808 if (ret)
809 return -ENXIO;
810 }
811 if (gpmc_capability & GPMC_HAS_WR_ACCESS) {
812 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0,
813 t->wr_access, GPMC_CD_FCLK,
814 "wr_access");
815 if (ret)
816 return -ENXIO;
817 }
818
819 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
820 l &= ~0x03;
821 l |= (div - 1);
822 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
823
824 ret = 0;
825 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19,
826 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
827 t->wait_monitoring, GPMC_CD_CLK,
828 "wait_monitoring");
829 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26,
830 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
831 t->clk_activation, GPMC_CD_FCLK,
832 "clk_activation");
833 if (ret)
834 return -ENXIO;
835
836 #ifdef CONFIG_OMAP_GPMC_DEBUG
837 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
838 cs, (div * gpmc_get_fclk_period()) / 1000, div);
839 #endif
840
841 gpmc_cs_bool_timings(cs, &t->bool_timings);
842 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
843
844 return 0;
845 }
846
gpmc_cs_set_memconf(int cs,u32 base,u32 size)847 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
848 {
849 u32 l;
850 u32 mask;
851
852 /*
853 * Ensure that base address is aligned on a
854 * boundary equal to or greater than size.
855 */
856 if (base & (size - 1))
857 return -EINVAL;
858
859 base >>= GPMC_CHUNK_SHIFT;
860 mask = (1 << GPMC_SECTION_SHIFT) - size;
861 mask >>= GPMC_CHUNK_SHIFT;
862 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
863
864 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
865 l &= ~GPMC_CONFIG7_MASK;
866 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
867 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
868 l |= GPMC_CONFIG7_CSVALID;
869 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
870
871 return 0;
872 }
873
gpmc_cs_enable_mem(int cs)874 static void gpmc_cs_enable_mem(int cs)
875 {
876 u32 l;
877
878 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
879 l |= GPMC_CONFIG7_CSVALID;
880 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
881 }
882
gpmc_cs_disable_mem(int cs)883 static void gpmc_cs_disable_mem(int cs)
884 {
885 u32 l;
886
887 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
888 l &= ~GPMC_CONFIG7_CSVALID;
889 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
890 }
891
gpmc_cs_get_memconf(int cs,u32 * base,u32 * size)892 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
893 {
894 u32 l;
895 u32 mask;
896
897 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
898 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
899 mask = (l >> 8) & 0x0f;
900 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
901 }
902
gpmc_cs_mem_enabled(int cs)903 static int gpmc_cs_mem_enabled(int cs)
904 {
905 u32 l;
906
907 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
908 return l & GPMC_CONFIG7_CSVALID;
909 }
910
gpmc_cs_set_reserved(int cs,int reserved)911 static void gpmc_cs_set_reserved(int cs, int reserved)
912 {
913 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
914
915 gpmc->flags |= GPMC_CS_RESERVED;
916 }
917
gpmc_cs_reserved(int cs)918 static bool gpmc_cs_reserved(int cs)
919 {
920 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
921
922 return gpmc->flags & GPMC_CS_RESERVED;
923 }
924
gpmc_mem_align(unsigned long size)925 static unsigned long gpmc_mem_align(unsigned long size)
926 {
927 int order;
928
929 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
930 order = GPMC_CHUNK_SHIFT - 1;
931 do {
932 size >>= 1;
933 order++;
934 } while (size);
935 size = 1 << order;
936 return size;
937 }
938
gpmc_cs_insert_mem(int cs,unsigned long base,unsigned long size)939 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
940 {
941 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
942 struct resource *res = &gpmc->mem;
943 int r;
944
945 size = gpmc_mem_align(size);
946 spin_lock(&gpmc_mem_lock);
947 res->start = base;
948 res->end = base + size - 1;
949 r = request_resource(&gpmc_mem_root, res);
950 spin_unlock(&gpmc_mem_lock);
951
952 return r;
953 }
954
gpmc_cs_delete_mem(int cs)955 static int gpmc_cs_delete_mem(int cs)
956 {
957 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
958 struct resource *res = &gpmc->mem;
959 int r;
960
961 spin_lock(&gpmc_mem_lock);
962 r = release_resource(res);
963 res->start = 0;
964 res->end = 0;
965 spin_unlock(&gpmc_mem_lock);
966
967 return r;
968 }
969
gpmc_cs_request(int cs,unsigned long size,unsigned long * base)970 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
971 {
972 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
973 struct resource *res = &gpmc->mem;
974 int r = -1;
975
976 if (cs >= gpmc_cs_num) {
977 pr_err("%s: requested chip-select is disabled\n", __func__);
978 return -ENODEV;
979 }
980 size = gpmc_mem_align(size);
981 if (size > (1 << GPMC_SECTION_SHIFT))
982 return -ENOMEM;
983
984 spin_lock(&gpmc_mem_lock);
985 if (gpmc_cs_reserved(cs)) {
986 r = -EBUSY;
987 goto out;
988 }
989 if (gpmc_cs_mem_enabled(cs))
990 r = adjust_resource(res, res->start & ~(size - 1), size);
991 if (r < 0)
992 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
993 size, NULL, NULL);
994 if (r < 0)
995 goto out;
996
997 /* Disable CS while changing base address and size mask */
998 gpmc_cs_disable_mem(cs);
999
1000 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1001 if (r < 0) {
1002 release_resource(res);
1003 goto out;
1004 }
1005
1006 /* Enable CS */
1007 gpmc_cs_enable_mem(cs);
1008 *base = res->start;
1009 gpmc_cs_set_reserved(cs, 1);
1010 out:
1011 spin_unlock(&gpmc_mem_lock);
1012 return r;
1013 }
1014 EXPORT_SYMBOL(gpmc_cs_request);
1015
gpmc_cs_free(int cs)1016 void gpmc_cs_free(int cs)
1017 {
1018 struct gpmc_cs_data *gpmc;
1019 struct resource *res;
1020
1021 spin_lock(&gpmc_mem_lock);
1022 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1023 WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs);
1024 spin_unlock(&gpmc_mem_lock);
1025 return;
1026 }
1027 gpmc = &gpmc_cs[cs];
1028 res = &gpmc->mem;
1029
1030 gpmc_cs_disable_mem(cs);
1031 if (res->flags)
1032 release_resource(res);
1033 gpmc_cs_set_reserved(cs, 0);
1034 spin_unlock(&gpmc_mem_lock);
1035 }
1036 EXPORT_SYMBOL(gpmc_cs_free);
1037
1038 /**
1039 * gpmc_configure - write request to configure gpmc
1040 * @cmd: command type
1041 * @wval: value to write
1042 * @return status of the operation
1043 */
gpmc_configure(int cmd,int wval)1044 int gpmc_configure(int cmd, int wval)
1045 {
1046 u32 regval;
1047
1048 switch (cmd) {
1049 case GPMC_CONFIG_WP:
1050 regval = gpmc_read_reg(GPMC_CONFIG);
1051 if (wval)
1052 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1053 else
1054 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
1055 gpmc_write_reg(GPMC_CONFIG, regval);
1056 break;
1057
1058 default:
1059 pr_err("%s: command not supported\n", __func__);
1060 return -EINVAL;
1061 }
1062
1063 return 0;
1064 }
1065 EXPORT_SYMBOL(gpmc_configure);
1066
gpmc_nand_writebuffer_empty(void)1067 static bool gpmc_nand_writebuffer_empty(void)
1068 {
1069 if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1070 return true;
1071
1072 return false;
1073 }
1074
1075 static struct gpmc_nand_ops nand_ops = {
1076 .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1077 };
1078
1079 /**
1080 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1081 * @reg: the GPMC NAND register map exclusive for NAND use.
1082 * @cs: GPMC chip select number on which the NAND sits. The
1083 * register map returned will be specific to this chip select.
1084 *
1085 * Returns NULL on error e.g. invalid cs.
1086 */
gpmc_omap_get_nand_ops(struct gpmc_nand_regs * reg,int cs)1087 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1088 {
1089 int i;
1090
1091 if (cs >= gpmc_cs_num)
1092 return NULL;
1093
1094 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1095 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1096 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1097 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1098 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1099 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1100 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1101 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1102 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1103 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1104 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1105 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1106 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1107 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1108
1109 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1110 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1111 GPMC_BCH_SIZE * i;
1112 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1113 GPMC_BCH_SIZE * i;
1114 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1115 GPMC_BCH_SIZE * i;
1116 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1117 GPMC_BCH_SIZE * i;
1118 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1119 i * GPMC_BCH_SIZE;
1120 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1121 i * GPMC_BCH_SIZE;
1122 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1123 i * GPMC_BCH_SIZE;
1124 }
1125
1126 return &nand_ops;
1127 }
1128 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1129
gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings * t,struct gpmc_settings * s,int freq,int latency)1130 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1131 struct gpmc_settings *s,
1132 int freq, int latency)
1133 {
1134 struct gpmc_device_timings dev_t;
1135 const int t_cer = 15;
1136 const int t_avdp = 12;
1137 const int t_cez = 20; /* max of t_cez, t_oez */
1138 const int t_wpl = 40;
1139 const int t_wph = 30;
1140 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1141
1142 switch (freq) {
1143 case 104:
1144 min_gpmc_clk_period = 9600; /* 104 MHz */
1145 t_ces = 3;
1146 t_avds = 4;
1147 t_avdh = 2;
1148 t_ach = 3;
1149 t_aavdh = 6;
1150 t_rdyo = 6;
1151 break;
1152 case 83:
1153 min_gpmc_clk_period = 12000; /* 83 MHz */
1154 t_ces = 5;
1155 t_avds = 4;
1156 t_avdh = 2;
1157 t_ach = 6;
1158 t_aavdh = 6;
1159 t_rdyo = 9;
1160 break;
1161 case 66:
1162 min_gpmc_clk_period = 15000; /* 66 MHz */
1163 t_ces = 6;
1164 t_avds = 5;
1165 t_avdh = 2;
1166 t_ach = 6;
1167 t_aavdh = 6;
1168 t_rdyo = 11;
1169 break;
1170 default:
1171 min_gpmc_clk_period = 18500; /* 54 MHz */
1172 t_ces = 7;
1173 t_avds = 7;
1174 t_avdh = 7;
1175 t_ach = 9;
1176 t_aavdh = 7;
1177 t_rdyo = 15;
1178 break;
1179 }
1180
1181 /* Set synchronous read timings */
1182 memset(&dev_t, 0, sizeof(dev_t));
1183
1184 if (!s->sync_write) {
1185 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1186 dev_t.t_wpl = t_wpl * 1000;
1187 dev_t.t_wph = t_wph * 1000;
1188 dev_t.t_aavdh = t_aavdh * 1000;
1189 }
1190 dev_t.ce_xdelay = true;
1191 dev_t.avd_xdelay = true;
1192 dev_t.oe_xdelay = true;
1193 dev_t.we_xdelay = true;
1194 dev_t.clk = min_gpmc_clk_period;
1195 dev_t.t_bacc = dev_t.clk;
1196 dev_t.t_ces = t_ces * 1000;
1197 dev_t.t_avds = t_avds * 1000;
1198 dev_t.t_avdh = t_avdh * 1000;
1199 dev_t.t_ach = t_ach * 1000;
1200 dev_t.cyc_iaa = (latency + 1);
1201 dev_t.t_cez_r = t_cez * 1000;
1202 dev_t.t_cez_w = dev_t.t_cez_r;
1203 dev_t.cyc_aavdh_oe = 1;
1204 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1205
1206 gpmc_calc_timings(t, s, &dev_t);
1207 }
1208
gpmc_omap_onenand_set_timings(struct device * dev,int cs,int freq,int latency,struct gpmc_onenand_info * info)1209 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1210 int latency,
1211 struct gpmc_onenand_info *info)
1212 {
1213 int ret;
1214 struct gpmc_timings gpmc_t;
1215 struct gpmc_settings gpmc_s;
1216
1217 gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1218
1219 info->sync_read = gpmc_s.sync_read;
1220 info->sync_write = gpmc_s.sync_write;
1221 info->burst_len = gpmc_s.burst_len;
1222
1223 if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1224 return 0;
1225
1226 gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1227
1228 ret = gpmc_cs_program_settings(cs, &gpmc_s);
1229 if (ret < 0)
1230 return ret;
1231
1232 return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1233 }
1234 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1235
gpmc_get_client_irq(unsigned int irq_config)1236 int gpmc_get_client_irq(unsigned int irq_config)
1237 {
1238 if (!gpmc_irq_domain) {
1239 pr_warn("%s called before GPMC IRQ domain available\n",
1240 __func__);
1241 return 0;
1242 }
1243
1244 /* we restrict this to NAND IRQs only */
1245 if (irq_config >= GPMC_NR_NAND_IRQS)
1246 return 0;
1247
1248 return irq_create_mapping(gpmc_irq_domain, irq_config);
1249 }
1250
gpmc_irq_endis(unsigned long hwirq,bool endis)1251 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1252 {
1253 u32 regval;
1254
1255 /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1256 if (hwirq >= GPMC_NR_NAND_IRQS)
1257 hwirq += 8 - GPMC_NR_NAND_IRQS;
1258
1259 regval = gpmc_read_reg(GPMC_IRQENABLE);
1260 if (endis)
1261 regval |= BIT(hwirq);
1262 else
1263 regval &= ~BIT(hwirq);
1264 gpmc_write_reg(GPMC_IRQENABLE, regval);
1265
1266 return 0;
1267 }
1268
gpmc_irq_disable(struct irq_data * p)1269 static void gpmc_irq_disable(struct irq_data *p)
1270 {
1271 gpmc_irq_endis(p->hwirq, false);
1272 }
1273
gpmc_irq_enable(struct irq_data * p)1274 static void gpmc_irq_enable(struct irq_data *p)
1275 {
1276 gpmc_irq_endis(p->hwirq, true);
1277 }
1278
gpmc_irq_mask(struct irq_data * d)1279 static void gpmc_irq_mask(struct irq_data *d)
1280 {
1281 gpmc_irq_endis(d->hwirq, false);
1282 }
1283
gpmc_irq_unmask(struct irq_data * d)1284 static void gpmc_irq_unmask(struct irq_data *d)
1285 {
1286 gpmc_irq_endis(d->hwirq, true);
1287 }
1288
gpmc_irq_edge_config(unsigned long hwirq,bool rising_edge)1289 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1290 {
1291 u32 regval;
1292
1293 /* NAND IRQs polarity is not configurable */
1294 if (hwirq < GPMC_NR_NAND_IRQS)
1295 return;
1296
1297 /* WAITPIN starts at BIT 8 */
1298 hwirq += 8 - GPMC_NR_NAND_IRQS;
1299
1300 regval = gpmc_read_reg(GPMC_CONFIG);
1301 if (rising_edge)
1302 regval &= ~BIT(hwirq);
1303 else
1304 regval |= BIT(hwirq);
1305
1306 gpmc_write_reg(GPMC_CONFIG, regval);
1307 }
1308
gpmc_irq_ack(struct irq_data * d)1309 static void gpmc_irq_ack(struct irq_data *d)
1310 {
1311 unsigned int hwirq = d->hwirq;
1312
1313 /* skip reserved bits */
1314 if (hwirq >= GPMC_NR_NAND_IRQS)
1315 hwirq += 8 - GPMC_NR_NAND_IRQS;
1316
1317 /* Setting bit to 1 clears (or Acks) the interrupt */
1318 gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1319 }
1320
gpmc_irq_set_type(struct irq_data * d,unsigned int trigger)1321 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1322 {
1323 /* can't set type for NAND IRQs */
1324 if (d->hwirq < GPMC_NR_NAND_IRQS)
1325 return -EINVAL;
1326
1327 /* We can support either rising or falling edge at a time */
1328 if (trigger == IRQ_TYPE_EDGE_FALLING)
1329 gpmc_irq_edge_config(d->hwirq, false);
1330 else if (trigger == IRQ_TYPE_EDGE_RISING)
1331 gpmc_irq_edge_config(d->hwirq, true);
1332 else
1333 return -EINVAL;
1334
1335 return 0;
1336 }
1337
gpmc_irq_map(struct irq_domain * d,unsigned int virq,irq_hw_number_t hw)1338 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1339 irq_hw_number_t hw)
1340 {
1341 struct gpmc_device *gpmc = d->host_data;
1342
1343 irq_set_chip_data(virq, gpmc);
1344 if (hw < GPMC_NR_NAND_IRQS) {
1345 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1346 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1347 handle_simple_irq);
1348 } else {
1349 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1350 handle_edge_irq);
1351 }
1352
1353 return 0;
1354 }
1355
1356 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1357 .map = gpmc_irq_map,
1358 .xlate = irq_domain_xlate_twocell,
1359 };
1360
gpmc_handle_irq(int irq,void * data)1361 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1362 {
1363 int hwirq, virq;
1364 u32 regval, regvalx;
1365 struct gpmc_device *gpmc = data;
1366
1367 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1368 regvalx = regval;
1369
1370 if (!regval)
1371 return IRQ_NONE;
1372
1373 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1374 /* skip reserved status bits */
1375 if (hwirq == GPMC_NR_NAND_IRQS)
1376 regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1377
1378 if (regvalx & BIT(hwirq)) {
1379 virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1380 if (!virq) {
1381 dev_warn(gpmc->dev,
1382 "spurious irq detected hwirq %d, virq %d\n",
1383 hwirq, virq);
1384 }
1385
1386 generic_handle_irq(virq);
1387 }
1388 }
1389
1390 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1391
1392 return IRQ_HANDLED;
1393 }
1394
gpmc_setup_irq(struct gpmc_device * gpmc)1395 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1396 {
1397 u32 regval;
1398 int rc;
1399
1400 /* Disable interrupts */
1401 gpmc_write_reg(GPMC_IRQENABLE, 0);
1402
1403 /* clear interrupts */
1404 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1405 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1406
1407 gpmc->irq_chip.name = "gpmc";
1408 gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1409 gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1410 gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1411 gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1412 gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1413 gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1414
1415 gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1416 gpmc->nirqs,
1417 &gpmc_irq_domain_ops,
1418 gpmc);
1419 if (!gpmc_irq_domain) {
1420 dev_err(gpmc->dev, "IRQ domain add failed\n");
1421 return -ENODEV;
1422 }
1423
1424 rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1425 if (rc) {
1426 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1427 gpmc->irq, rc);
1428 irq_domain_remove(gpmc_irq_domain);
1429 gpmc_irq_domain = NULL;
1430 }
1431
1432 return rc;
1433 }
1434
gpmc_free_irq(struct gpmc_device * gpmc)1435 static int gpmc_free_irq(struct gpmc_device *gpmc)
1436 {
1437 int hwirq;
1438
1439 free_irq(gpmc->irq, gpmc);
1440
1441 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1442 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1443
1444 irq_domain_remove(gpmc_irq_domain);
1445 gpmc_irq_domain = NULL;
1446
1447 return 0;
1448 }
1449
gpmc_mem_exit(void)1450 static void gpmc_mem_exit(void)
1451 {
1452 int cs;
1453
1454 for (cs = 0; cs < gpmc_cs_num; cs++) {
1455 if (!gpmc_cs_mem_enabled(cs))
1456 continue;
1457 gpmc_cs_delete_mem(cs);
1458 }
1459 }
1460
gpmc_mem_init(struct gpmc_device * gpmc)1461 static void gpmc_mem_init(struct gpmc_device *gpmc)
1462 {
1463 int cs;
1464
1465 if (!gpmc->data) {
1466 /* All legacy devices have same data IO window */
1467 gpmc_mem_root.start = GPMC_MEM_START;
1468 gpmc_mem_root.end = GPMC_MEM_END;
1469 } else {
1470 gpmc_mem_root.start = gpmc->data->start;
1471 gpmc_mem_root.end = gpmc->data->end;
1472 }
1473
1474 /* Reserve all regions that has been set up by bootloader */
1475 for (cs = 0; cs < gpmc_cs_num; cs++) {
1476 u32 base, size;
1477
1478 if (!gpmc_cs_mem_enabled(cs))
1479 continue;
1480 gpmc_cs_get_memconf(cs, &base, &size);
1481 if (gpmc_cs_insert_mem(cs, base, size)) {
1482 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1483 __func__, cs, base, base + size);
1484 gpmc_cs_disable_mem(cs);
1485 }
1486 }
1487 }
1488
gpmc_round_ps_to_sync_clk(u32 time_ps,u32 sync_clk)1489 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1490 {
1491 u32 temp;
1492 int div;
1493
1494 div = gpmc_calc_divider(sync_clk);
1495 temp = gpmc_ps_to_ticks(time_ps);
1496 temp = (temp + div - 1) / div;
1497 return gpmc_ticks_to_ps(temp * div);
1498 }
1499
1500 /* XXX: can the cycles be avoided ? */
gpmc_calc_sync_read_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1501 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1502 struct gpmc_device_timings *dev_t,
1503 bool mux)
1504 {
1505 u32 temp;
1506
1507 /* adv_rd_off */
1508 temp = dev_t->t_avdp_r;
1509 /* XXX: mux check required ? */
1510 if (mux) {
1511 /* XXX: t_avdp not to be required for sync, only added for tusb
1512 * this indirectly necessitates requirement of t_avdp_r and
1513 * t_avdp_w instead of having a single t_avdp
1514 */
1515 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1516 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1517 }
1518 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1519
1520 /* oe_on */
1521 temp = dev_t->t_oeasu; /* XXX: remove this ? */
1522 if (mux) {
1523 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1524 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1525 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1526 }
1527 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1528
1529 /* access */
1530 /* XXX: any scope for improvement ?, by combining oe_on
1531 * and clk_activation, need to check whether
1532 * access = clk_activation + round to sync clk ?
1533 */
1534 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1535 temp += gpmc_t->clk_activation;
1536 if (dev_t->cyc_oe)
1537 temp = max_t(u32, temp, gpmc_t->oe_on +
1538 gpmc_ticks_to_ps(dev_t->cyc_oe));
1539 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1540
1541 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1542 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1543
1544 /* rd_cycle */
1545 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1546 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1547 gpmc_t->access;
1548 /* XXX: barter t_ce_rdyz with t_cez_r ? */
1549 if (dev_t->t_ce_rdyz)
1550 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1551 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1552
1553 return 0;
1554 }
1555
gpmc_calc_sync_write_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1556 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1557 struct gpmc_device_timings *dev_t,
1558 bool mux)
1559 {
1560 u32 temp;
1561
1562 /* adv_wr_off */
1563 temp = dev_t->t_avdp_w;
1564 if (mux) {
1565 temp = max_t(u32, temp,
1566 gpmc_t->clk_activation + dev_t->t_avdh);
1567 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1568 }
1569 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1570
1571 /* wr_data_mux_bus */
1572 temp = max_t(u32, dev_t->t_weasu,
1573 gpmc_t->clk_activation + dev_t->t_rdyo);
1574 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1575 * and in that case remember to handle we_on properly
1576 */
1577 if (mux) {
1578 temp = max_t(u32, temp,
1579 gpmc_t->adv_wr_off + dev_t->t_aavdh);
1580 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1581 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1582 }
1583 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1584
1585 /* we_on */
1586 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1587 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1588 else
1589 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1590
1591 /* wr_access */
1592 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1593 gpmc_t->wr_access = gpmc_t->access;
1594
1595 /* we_off */
1596 temp = gpmc_t->we_on + dev_t->t_wpl;
1597 temp = max_t(u32, temp,
1598 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1599 temp = max_t(u32, temp,
1600 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1601 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1602
1603 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1604 dev_t->t_wph);
1605
1606 /* wr_cycle */
1607 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1608 temp += gpmc_t->wr_access;
1609 /* XXX: barter t_ce_rdyz with t_cez_w ? */
1610 if (dev_t->t_ce_rdyz)
1611 temp = max_t(u32, temp,
1612 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1613 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1614
1615 return 0;
1616 }
1617
gpmc_calc_async_read_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1618 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1619 struct gpmc_device_timings *dev_t,
1620 bool mux)
1621 {
1622 u32 temp;
1623
1624 /* adv_rd_off */
1625 temp = dev_t->t_avdp_r;
1626 if (mux)
1627 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1628 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1629
1630 /* oe_on */
1631 temp = dev_t->t_oeasu;
1632 if (mux)
1633 temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
1634 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1635
1636 /* access */
1637 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1638 gpmc_t->oe_on + dev_t->t_oe);
1639 temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
1640 temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
1641 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1642
1643 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1644 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1645
1646 /* rd_cycle */
1647 temp = max_t(u32, dev_t->t_rd_cycle,
1648 gpmc_t->cs_rd_off + dev_t->t_cez_r);
1649 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1650 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1651
1652 return 0;
1653 }
1654
gpmc_calc_async_write_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1655 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1656 struct gpmc_device_timings *dev_t,
1657 bool mux)
1658 {
1659 u32 temp;
1660
1661 /* adv_wr_off */
1662 temp = dev_t->t_avdp_w;
1663 if (mux)
1664 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1665 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1666
1667 /* wr_data_mux_bus */
1668 temp = dev_t->t_weasu;
1669 if (mux) {
1670 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1671 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1672 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1673 }
1674 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1675
1676 /* we_on */
1677 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1678 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1679 else
1680 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1681
1682 /* we_off */
1683 temp = gpmc_t->we_on + dev_t->t_wpl;
1684 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1685
1686 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1687 dev_t->t_wph);
1688
1689 /* wr_cycle */
1690 temp = max_t(u32, dev_t->t_wr_cycle,
1691 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1692 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1693
1694 return 0;
1695 }
1696
gpmc_calc_sync_common_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t)1697 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1698 struct gpmc_device_timings *dev_t)
1699 {
1700 u32 temp;
1701
1702 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1703 gpmc_get_fclk_period();
1704
1705 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1706 dev_t->t_bacc,
1707 gpmc_t->sync_clk);
1708
1709 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1710 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1711
1712 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1713 return 0;
1714
1715 if (dev_t->ce_xdelay)
1716 gpmc_t->bool_timings.cs_extra_delay = true;
1717 if (dev_t->avd_xdelay)
1718 gpmc_t->bool_timings.adv_extra_delay = true;
1719 if (dev_t->oe_xdelay)
1720 gpmc_t->bool_timings.oe_extra_delay = true;
1721 if (dev_t->we_xdelay)
1722 gpmc_t->bool_timings.we_extra_delay = true;
1723
1724 return 0;
1725 }
1726
gpmc_calc_common_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool sync)1727 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1728 struct gpmc_device_timings *dev_t,
1729 bool sync)
1730 {
1731 u32 temp;
1732
1733 /* cs_on */
1734 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1735
1736 /* adv_on */
1737 temp = dev_t->t_avdasu;
1738 if (dev_t->t_ce_avd)
1739 temp = max_t(u32, temp,
1740 gpmc_t->cs_on + dev_t->t_ce_avd);
1741 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1742
1743 if (sync)
1744 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1745
1746 return 0;
1747 }
1748
1749 /*
1750 * TODO: remove this function once all peripherals are confirmed to
1751 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1752 * has to be modified to handle timings in ps instead of ns
1753 */
gpmc_convert_ps_to_ns(struct gpmc_timings * t)1754 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1755 {
1756 t->cs_on /= 1000;
1757 t->cs_rd_off /= 1000;
1758 t->cs_wr_off /= 1000;
1759 t->adv_on /= 1000;
1760 t->adv_rd_off /= 1000;
1761 t->adv_wr_off /= 1000;
1762 t->we_on /= 1000;
1763 t->we_off /= 1000;
1764 t->oe_on /= 1000;
1765 t->oe_off /= 1000;
1766 t->page_burst_access /= 1000;
1767 t->access /= 1000;
1768 t->rd_cycle /= 1000;
1769 t->wr_cycle /= 1000;
1770 t->bus_turnaround /= 1000;
1771 t->cycle2cycle_delay /= 1000;
1772 t->wait_monitoring /= 1000;
1773 t->clk_activation /= 1000;
1774 t->wr_access /= 1000;
1775 t->wr_data_mux_bus /= 1000;
1776 }
1777
gpmc_calc_timings(struct gpmc_timings * gpmc_t,struct gpmc_settings * gpmc_s,struct gpmc_device_timings * dev_t)1778 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1779 struct gpmc_settings *gpmc_s,
1780 struct gpmc_device_timings *dev_t)
1781 {
1782 bool mux = false, sync = false;
1783
1784 if (gpmc_s) {
1785 mux = gpmc_s->mux_add_data ? true : false;
1786 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1787 }
1788
1789 memset(gpmc_t, 0, sizeof(*gpmc_t));
1790
1791 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1792
1793 if (gpmc_s && gpmc_s->sync_read)
1794 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1795 else
1796 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1797
1798 if (gpmc_s && gpmc_s->sync_write)
1799 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1800 else
1801 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1802
1803 /* TODO: remove, see function definition */
1804 gpmc_convert_ps_to_ns(gpmc_t);
1805
1806 return 0;
1807 }
1808
1809 /**
1810 * gpmc_cs_program_settings - programs non-timing related settings
1811 * @cs: GPMC chip-select to program
1812 * @p: pointer to GPMC settings structure
1813 *
1814 * Programs non-timing related settings for a GPMC chip-select, such as
1815 * bus-width, burst configuration, etc. Function should be called once
1816 * for each chip-select that is being used and must be called before
1817 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1818 * register will be initialised to zero by this function. Returns 0 on
1819 * success and appropriate negative error code on failure.
1820 */
gpmc_cs_program_settings(int cs,struct gpmc_settings * p)1821 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1822 {
1823 u32 config1;
1824
1825 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1826 pr_err("%s: invalid width %d!", __func__, p->device_width);
1827 return -EINVAL;
1828 }
1829
1830 /* Address-data multiplexing not supported for NAND devices */
1831 if (p->device_nand && p->mux_add_data) {
1832 pr_err("%s: invalid configuration!\n", __func__);
1833 return -EINVAL;
1834 }
1835
1836 if ((p->mux_add_data > GPMC_MUX_AD) ||
1837 ((p->mux_add_data == GPMC_MUX_AAD) &&
1838 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1839 pr_err("%s: invalid multiplex configuration!\n", __func__);
1840 return -EINVAL;
1841 }
1842
1843 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1844 if (p->burst_read || p->burst_write) {
1845 switch (p->burst_len) {
1846 case GPMC_BURST_4:
1847 case GPMC_BURST_8:
1848 case GPMC_BURST_16:
1849 break;
1850 default:
1851 pr_err("%s: invalid page/burst-length (%d)\n",
1852 __func__, p->burst_len);
1853 return -EINVAL;
1854 }
1855 }
1856
1857 if (p->wait_pin > gpmc_nr_waitpins) {
1858 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1859 return -EINVAL;
1860 }
1861
1862 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1863
1864 if (p->sync_read)
1865 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1866 if (p->sync_write)
1867 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1868 if (p->wait_on_read)
1869 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1870 if (p->wait_on_write)
1871 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1872 if (p->wait_on_read || p->wait_on_write)
1873 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1874 if (p->device_nand)
1875 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1876 if (p->mux_add_data)
1877 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1878 if (p->burst_read)
1879 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1880 if (p->burst_write)
1881 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1882 if (p->burst_read || p->burst_write) {
1883 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1884 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1885 }
1886
1887 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1888
1889 return 0;
1890 }
1891
1892 #ifdef CONFIG_OF
gpmc_cs_set_name(int cs,const char * name)1893 static void gpmc_cs_set_name(int cs, const char *name)
1894 {
1895 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1896
1897 gpmc->name = name;
1898 }
1899
gpmc_cs_get_name(int cs)1900 static const char *gpmc_cs_get_name(int cs)
1901 {
1902 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1903
1904 return gpmc->name;
1905 }
1906
1907 /**
1908 * gpmc_cs_remap - remaps a chip-select physical base address
1909 * @cs: chip-select to remap
1910 * @base: physical base address to re-map chip-select to
1911 *
1912 * Re-maps a chip-select to a new physical base address specified by
1913 * "base". Returns 0 on success and appropriate negative error code
1914 * on failure.
1915 */
gpmc_cs_remap(int cs,u32 base)1916 static int gpmc_cs_remap(int cs, u32 base)
1917 {
1918 int ret;
1919 u32 old_base, size;
1920
1921 if (cs >= gpmc_cs_num) {
1922 pr_err("%s: requested chip-select is disabled\n", __func__);
1923 return -ENODEV;
1924 }
1925
1926 /*
1927 * Make sure we ignore any device offsets from the GPMC partition
1928 * allocated for the chip select and that the new base confirms
1929 * to the GPMC 16MB minimum granularity.
1930 */
1931 base &= ~(SZ_16M - 1);
1932
1933 gpmc_cs_get_memconf(cs, &old_base, &size);
1934 if (base == old_base)
1935 return 0;
1936
1937 ret = gpmc_cs_delete_mem(cs);
1938 if (ret < 0)
1939 return ret;
1940
1941 ret = gpmc_cs_insert_mem(cs, base, size);
1942 if (ret < 0)
1943 return ret;
1944
1945 ret = gpmc_cs_set_memconf(cs, base, size);
1946
1947 return ret;
1948 }
1949
1950 /**
1951 * gpmc_read_settings_dt - read gpmc settings from device-tree
1952 * @np: pointer to device-tree node for a gpmc child device
1953 * @p: pointer to gpmc settings structure
1954 *
1955 * Reads the GPMC settings for a GPMC child device from device-tree and
1956 * stores them in the GPMC settings structure passed. The GPMC settings
1957 * structure is initialised to zero by this function and so any
1958 * previously stored settings will be cleared.
1959 */
gpmc_read_settings_dt(struct device_node * np,struct gpmc_settings * p)1960 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1961 {
1962 memset(p, 0, sizeof(struct gpmc_settings));
1963
1964 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1965 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1966 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1967 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1968
1969 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1970 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1971 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1972 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1973 if (!p->burst_read && !p->burst_write)
1974 pr_warn("%s: page/burst-length set but not used!\n",
1975 __func__);
1976 }
1977
1978 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1979 p->wait_on_read = of_property_read_bool(np,
1980 "gpmc,wait-on-read");
1981 p->wait_on_write = of_property_read_bool(np,
1982 "gpmc,wait-on-write");
1983 if (!p->wait_on_read && !p->wait_on_write)
1984 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1985 __func__);
1986 }
1987 }
1988
gpmc_read_timings_dt(struct device_node * np,struct gpmc_timings * gpmc_t)1989 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1990 struct gpmc_timings *gpmc_t)
1991 {
1992 struct gpmc_bool_timings *p;
1993
1994 if (!np || !gpmc_t)
1995 return;
1996
1997 memset(gpmc_t, 0, sizeof(*gpmc_t));
1998
1999 /* minimum clock period for syncronous mode */
2000 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
2001
2002 /* chip select timtings */
2003 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
2004 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
2005 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
2006
2007 /* ADV signal timings */
2008 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
2009 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
2010 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
2011 of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
2012 &gpmc_t->adv_aad_mux_on);
2013 of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
2014 &gpmc_t->adv_aad_mux_rd_off);
2015 of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
2016 &gpmc_t->adv_aad_mux_wr_off);
2017
2018 /* WE signal timings */
2019 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
2020 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
2021
2022 /* OE signal timings */
2023 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
2024 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
2025 of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
2026 &gpmc_t->oe_aad_mux_on);
2027 of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
2028 &gpmc_t->oe_aad_mux_off);
2029
2030 /* access and cycle timings */
2031 of_property_read_u32(np, "gpmc,page-burst-access-ns",
2032 &gpmc_t->page_burst_access);
2033 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
2034 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
2035 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
2036 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
2037 &gpmc_t->bus_turnaround);
2038 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
2039 &gpmc_t->cycle2cycle_delay);
2040 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
2041 &gpmc_t->wait_monitoring);
2042 of_property_read_u32(np, "gpmc,clk-activation-ns",
2043 &gpmc_t->clk_activation);
2044
2045 /* only applicable to OMAP3+ */
2046 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
2047 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
2048 &gpmc_t->wr_data_mux_bus);
2049
2050 /* bool timing parameters */
2051 p = &gpmc_t->bool_timings;
2052
2053 p->cycle2cyclediffcsen =
2054 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2055 p->cycle2cyclesamecsen =
2056 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2057 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2058 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2059 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2060 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2061 p->time_para_granularity =
2062 of_property_read_bool(np, "gpmc,time-para-granularity");
2063 }
2064
2065 /**
2066 * gpmc_probe_generic_child - configures the gpmc for a child device
2067 * @pdev: pointer to gpmc platform device
2068 * @child: pointer to device-tree node for child device
2069 *
2070 * Allocates and configures a GPMC chip-select for a child device.
2071 * Returns 0 on success and appropriate negative error code on failure.
2072 */
gpmc_probe_generic_child(struct platform_device * pdev,struct device_node * child)2073 static int gpmc_probe_generic_child(struct platform_device *pdev,
2074 struct device_node *child)
2075 {
2076 struct gpmc_settings gpmc_s;
2077 struct gpmc_timings gpmc_t;
2078 struct resource res;
2079 unsigned long base;
2080 const char *name;
2081 int ret, cs;
2082 u32 val;
2083 struct gpio_desc *waitpin_desc = NULL;
2084 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2085
2086 if (of_property_read_u32(child, "reg", &cs) < 0) {
2087 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2088 child);
2089 return -ENODEV;
2090 }
2091
2092 if (of_address_to_resource(child, 0, &res) < 0) {
2093 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2094 child);
2095 return -ENODEV;
2096 }
2097
2098 /*
2099 * Check if we have multiple instances of the same device
2100 * on a single chip select. If so, use the already initialized
2101 * timings.
2102 */
2103 name = gpmc_cs_get_name(cs);
2104 if (name && of_node_name_eq(child, name))
2105 goto no_timings;
2106
2107 ret = gpmc_cs_request(cs, resource_size(&res), &base);
2108 if (ret < 0) {
2109 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2110 return ret;
2111 }
2112 gpmc_cs_set_name(cs, child->full_name);
2113
2114 gpmc_read_settings_dt(child, &gpmc_s);
2115 gpmc_read_timings_dt(child, &gpmc_t);
2116
2117 /*
2118 * For some GPMC devices we still need to rely on the bootloader
2119 * timings because the devices can be connected via FPGA.
2120 * REVISIT: Add timing support from slls644g.pdf.
2121 */
2122 if (!gpmc_t.cs_rd_off) {
2123 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2124 cs);
2125 gpmc_cs_show_timings(cs,
2126 "please add GPMC bootloader timings to .dts");
2127 goto no_timings;
2128 }
2129
2130 /* CS must be disabled while making changes to gpmc configuration */
2131 gpmc_cs_disable_mem(cs);
2132
2133 /*
2134 * FIXME: gpmc_cs_request() will map the CS to an arbitrary
2135 * location in the gpmc address space. When booting with
2136 * device-tree we want the NOR flash to be mapped to the
2137 * location specified in the device-tree blob. So remap the
2138 * CS to this location. Once DT migration is complete should
2139 * just make gpmc_cs_request() map a specific address.
2140 */
2141 ret = gpmc_cs_remap(cs, res.start);
2142 if (ret < 0) {
2143 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2144 cs, &res.start);
2145 if (res.start < GPMC_MEM_START) {
2146 dev_info(&pdev->dev,
2147 "GPMC CS %d start cannot be lesser than 0x%x\n",
2148 cs, GPMC_MEM_START);
2149 } else if (res.end > GPMC_MEM_END) {
2150 dev_info(&pdev->dev,
2151 "GPMC CS %d end cannot be greater than 0x%x\n",
2152 cs, GPMC_MEM_END);
2153 }
2154 goto err;
2155 }
2156
2157 if (of_node_name_eq(child, "nand")) {
2158 /* Warn about older DT blobs with no compatible property */
2159 if (!of_property_read_bool(child, "compatible")) {
2160 dev_warn(&pdev->dev,
2161 "Incompatible NAND node: missing compatible");
2162 ret = -EINVAL;
2163 goto err;
2164 }
2165 }
2166
2167 if (of_node_name_eq(child, "onenand")) {
2168 /* Warn about older DT blobs with no compatible property */
2169 if (!of_property_read_bool(child, "compatible")) {
2170 dev_warn(&pdev->dev,
2171 "Incompatible OneNAND node: missing compatible");
2172 ret = -EINVAL;
2173 goto err;
2174 }
2175 }
2176
2177 if (of_match_node(omap_nand_ids, child)) {
2178 /* NAND specific setup */
2179 val = 8;
2180 of_property_read_u32(child, "nand-bus-width", &val);
2181 switch (val) {
2182 case 8:
2183 gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2184 break;
2185 case 16:
2186 gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2187 break;
2188 default:
2189 dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
2190 child);
2191 ret = -EINVAL;
2192 goto err;
2193 }
2194
2195 /* disable write protect */
2196 gpmc_configure(GPMC_CONFIG_WP, 0);
2197 gpmc_s.device_nand = true;
2198 } else {
2199 ret = of_property_read_u32(child, "bank-width",
2200 &gpmc_s.device_width);
2201 if (ret < 0 && !gpmc_s.device_width) {
2202 dev_err(&pdev->dev,
2203 "%pOF has no 'gpmc,device-width' property\n",
2204 child);
2205 goto err;
2206 }
2207 }
2208
2209 /* Reserve wait pin if it is required and valid */
2210 if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2211 unsigned int wait_pin = gpmc_s.wait_pin;
2212
2213 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
2214 wait_pin, "WAITPIN",
2215 GPIO_ACTIVE_HIGH,
2216 GPIOD_IN);
2217 if (IS_ERR(waitpin_desc)) {
2218 dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2219 ret = PTR_ERR(waitpin_desc);
2220 goto err;
2221 }
2222 }
2223
2224 gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2225
2226 ret = gpmc_cs_program_settings(cs, &gpmc_s);
2227 if (ret < 0)
2228 goto err_cs;
2229
2230 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2231 if (ret) {
2232 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
2233 child);
2234 goto err_cs;
2235 }
2236
2237 /* Clear limited address i.e. enable A26-A11 */
2238 val = gpmc_read_reg(GPMC_CONFIG);
2239 val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2240 gpmc_write_reg(GPMC_CONFIG, val);
2241
2242 /* Enable CS region */
2243 gpmc_cs_enable_mem(cs);
2244
2245 no_timings:
2246
2247 /* create platform device, NULL on error or when disabled */
2248 if (!of_platform_device_create(child, NULL, &pdev->dev))
2249 goto err_child_fail;
2250
2251 /* create children and other common bus children */
2252 if (of_platform_default_populate(child, NULL, &pdev->dev))
2253 goto err_child_fail;
2254
2255 return 0;
2256
2257 err_child_fail:
2258
2259 dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
2260 ret = -ENODEV;
2261
2262 err_cs:
2263 gpiochip_free_own_desc(waitpin_desc);
2264 err:
2265 gpmc_cs_free(cs);
2266
2267 return ret;
2268 }
2269
2270 static const struct of_device_id gpmc_dt_ids[];
2271
gpmc_probe_dt(struct platform_device * pdev)2272 static int gpmc_probe_dt(struct platform_device *pdev)
2273 {
2274 int ret;
2275 const struct of_device_id *of_id =
2276 of_match_device(gpmc_dt_ids, &pdev->dev);
2277
2278 if (!of_id)
2279 return 0;
2280
2281 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2282 &gpmc_cs_num);
2283 if (ret < 0) {
2284 pr_err("%s: number of chip-selects not defined\n", __func__);
2285 return ret;
2286 } else if (gpmc_cs_num < 1) {
2287 pr_err("%s: all chip-selects are disabled\n", __func__);
2288 return -EINVAL;
2289 } else if (gpmc_cs_num > GPMC_CS_NUM) {
2290 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2291 __func__, GPMC_CS_NUM);
2292 return -EINVAL;
2293 }
2294
2295 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2296 &gpmc_nr_waitpins);
2297 if (ret < 0) {
2298 pr_err("%s: number of wait pins not found!\n", __func__);
2299 return ret;
2300 }
2301
2302 return 0;
2303 }
2304
gpmc_probe_dt_children(struct platform_device * pdev)2305 static void gpmc_probe_dt_children(struct platform_device *pdev)
2306 {
2307 int ret;
2308 struct device_node *child;
2309
2310 for_each_available_child_of_node(pdev->dev.of_node, child) {
2311 ret = gpmc_probe_generic_child(pdev, child);
2312 if (ret) {
2313 dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
2314 child, ret);
2315 }
2316 }
2317 }
2318 #else
gpmc_read_settings_dt(struct device_node * np,struct gpmc_settings * p)2319 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
2320 {
2321 memset(p, 0, sizeof(*p));
2322 }
gpmc_probe_dt(struct platform_device * pdev)2323 static int gpmc_probe_dt(struct platform_device *pdev)
2324 {
2325 return 0;
2326 }
2327
gpmc_probe_dt_children(struct platform_device * pdev)2328 static void gpmc_probe_dt_children(struct platform_device *pdev)
2329 {
2330 }
2331 #endif /* CONFIG_OF */
2332
gpmc_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)2333 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2334 {
2335 return 1; /* we're input only */
2336 }
2337
gpmc_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)2338 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2339 unsigned int offset)
2340 {
2341 return 0; /* we're input only */
2342 }
2343
gpmc_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)2344 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2345 unsigned int offset, int value)
2346 {
2347 return -EINVAL; /* we're input only */
2348 }
2349
gpmc_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)2350 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2351 int value)
2352 {
2353 }
2354
gpmc_gpio_get(struct gpio_chip * chip,unsigned int offset)2355 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2356 {
2357 u32 reg;
2358
2359 offset += 8;
2360
2361 reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2362
2363 return !!reg;
2364 }
2365
gpmc_gpio_init(struct gpmc_device * gpmc)2366 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2367 {
2368 int ret;
2369
2370 gpmc->gpio_chip.parent = gpmc->dev;
2371 gpmc->gpio_chip.owner = THIS_MODULE;
2372 gpmc->gpio_chip.label = DEVICE_NAME;
2373 gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2374 gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2375 gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2376 gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2377 gpmc->gpio_chip.set = gpmc_gpio_set;
2378 gpmc->gpio_chip.get = gpmc_gpio_get;
2379 gpmc->gpio_chip.base = -1;
2380
2381 ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
2382 if (ret < 0) {
2383 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2384 return ret;
2385 }
2386
2387 return 0;
2388 }
2389
omap3_gpmc_save_context(struct gpmc_device * gpmc)2390 static void omap3_gpmc_save_context(struct gpmc_device *gpmc)
2391 {
2392 struct omap3_gpmc_regs *gpmc_context;
2393 int i;
2394
2395 if (!gpmc || !gpmc_base)
2396 return;
2397
2398 gpmc_context = &gpmc->context;
2399
2400 gpmc_context->sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2401 gpmc_context->irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2402 gpmc_context->timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2403 gpmc_context->config = gpmc_read_reg(GPMC_CONFIG);
2404 gpmc_context->prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2405 gpmc_context->prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2406 gpmc_context->prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2407 for (i = 0; i < gpmc_cs_num; i++) {
2408 gpmc_context->cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2409 if (gpmc_context->cs_context[i].is_valid) {
2410 gpmc_context->cs_context[i].config1 =
2411 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2412 gpmc_context->cs_context[i].config2 =
2413 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2414 gpmc_context->cs_context[i].config3 =
2415 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2416 gpmc_context->cs_context[i].config4 =
2417 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2418 gpmc_context->cs_context[i].config5 =
2419 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2420 gpmc_context->cs_context[i].config6 =
2421 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2422 gpmc_context->cs_context[i].config7 =
2423 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2424 }
2425 }
2426 }
2427
omap3_gpmc_restore_context(struct gpmc_device * gpmc)2428 static void omap3_gpmc_restore_context(struct gpmc_device *gpmc)
2429 {
2430 struct omap3_gpmc_regs *gpmc_context;
2431 int i;
2432
2433 if (!gpmc || !gpmc_base)
2434 return;
2435
2436 gpmc_context = &gpmc->context;
2437
2438 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context->sysconfig);
2439 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context->irqenable);
2440 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context->timeout_ctrl);
2441 gpmc_write_reg(GPMC_CONFIG, gpmc_context->config);
2442 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context->prefetch_config1);
2443 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context->prefetch_config2);
2444 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context->prefetch_control);
2445 for (i = 0; i < gpmc_cs_num; i++) {
2446 if (gpmc_context->cs_context[i].is_valid) {
2447 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2448 gpmc_context->cs_context[i].config1);
2449 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2450 gpmc_context->cs_context[i].config2);
2451 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2452 gpmc_context->cs_context[i].config3);
2453 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2454 gpmc_context->cs_context[i].config4);
2455 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2456 gpmc_context->cs_context[i].config5);
2457 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2458 gpmc_context->cs_context[i].config6);
2459 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2460 gpmc_context->cs_context[i].config7);
2461 } else {
2462 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, 0);
2463 }
2464 }
2465 }
2466
omap_gpmc_context_notifier(struct notifier_block * nb,unsigned long cmd,void * v)2467 static int omap_gpmc_context_notifier(struct notifier_block *nb,
2468 unsigned long cmd, void *v)
2469 {
2470 struct gpmc_device *gpmc;
2471
2472 gpmc = container_of(nb, struct gpmc_device, nb);
2473 if (gpmc->is_suspended || pm_runtime_suspended(gpmc->dev))
2474 return NOTIFY_OK;
2475
2476 switch (cmd) {
2477 case CPU_CLUSTER_PM_ENTER:
2478 omap3_gpmc_save_context(gpmc);
2479 break;
2480 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
2481 break;
2482 case CPU_CLUSTER_PM_EXIT:
2483 omap3_gpmc_restore_context(gpmc);
2484 break;
2485 }
2486
2487 return NOTIFY_OK;
2488 }
2489
gpmc_probe(struct platform_device * pdev)2490 static int gpmc_probe(struct platform_device *pdev)
2491 {
2492 int rc;
2493 u32 l;
2494 struct resource *res;
2495 struct gpmc_device *gpmc;
2496
2497 gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2498 if (!gpmc)
2499 return -ENOMEM;
2500
2501 gpmc->dev = &pdev->dev;
2502 platform_set_drvdata(pdev, gpmc);
2503
2504 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
2505 if (!res) {
2506 /* legacy DT */
2507 gpmc_base = devm_platform_ioremap_resource(pdev, 0);
2508 if (IS_ERR(gpmc_base))
2509 return PTR_ERR(gpmc_base);
2510 } else {
2511 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2512 if (IS_ERR(gpmc_base))
2513 return PTR_ERR(gpmc_base);
2514
2515 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "data");
2516 if (!res) {
2517 dev_err(&pdev->dev, "couldn't get data reg resource\n");
2518 return -ENOENT;
2519 }
2520
2521 gpmc->data = res;
2522 }
2523
2524 gpmc->irq = platform_get_irq(pdev, 0);
2525 if (gpmc->irq < 0)
2526 return gpmc->irq;
2527
2528 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2529 if (IS_ERR(gpmc_l3_clk)) {
2530 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2531 return PTR_ERR(gpmc_l3_clk);
2532 }
2533
2534 if (!clk_get_rate(gpmc_l3_clk)) {
2535 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2536 return -EINVAL;
2537 }
2538
2539 if (pdev->dev.of_node) {
2540 rc = gpmc_probe_dt(pdev);
2541 if (rc)
2542 return rc;
2543 } else {
2544 gpmc_cs_num = GPMC_CS_NUM;
2545 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2546 }
2547
2548 pm_runtime_enable(&pdev->dev);
2549 pm_runtime_get_sync(&pdev->dev);
2550
2551 l = gpmc_read_reg(GPMC_REVISION);
2552
2553 /*
2554 * FIXME: Once device-tree migration is complete the below flags
2555 * should be populated based upon the device-tree compatible
2556 * string. For now just use the IP revision. OMAP3+ devices have
2557 * the wr_access and wr_data_mux_bus register fields. OMAP4+
2558 * devices support the addr-addr-data multiplex protocol.
2559 *
2560 * GPMC IP revisions:
2561 * - OMAP24xx = 2.0
2562 * - OMAP3xxx = 5.0
2563 * - OMAP44xx/54xx/AM335x = 6.0
2564 */
2565 if (GPMC_REVISION_MAJOR(l) > 0x4)
2566 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2567 if (GPMC_REVISION_MAJOR(l) > 0x5)
2568 gpmc_capability |= GPMC_HAS_MUX_AAD;
2569 dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2570 GPMC_REVISION_MINOR(l));
2571
2572 gpmc_mem_init(gpmc);
2573 rc = gpmc_gpio_init(gpmc);
2574 if (rc)
2575 goto gpio_init_failed;
2576
2577 gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2578 rc = gpmc_setup_irq(gpmc);
2579 if (rc) {
2580 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2581 goto gpio_init_failed;
2582 }
2583
2584 gpmc_probe_dt_children(pdev);
2585
2586 gpmc->nb.notifier_call = omap_gpmc_context_notifier;
2587 cpu_pm_register_notifier(&gpmc->nb);
2588
2589 return 0;
2590
2591 gpio_init_failed:
2592 gpmc_mem_exit();
2593 pm_runtime_put_sync(&pdev->dev);
2594 pm_runtime_disable(&pdev->dev);
2595
2596 return rc;
2597 }
2598
gpmc_remove(struct platform_device * pdev)2599 static int gpmc_remove(struct platform_device *pdev)
2600 {
2601 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2602
2603 cpu_pm_unregister_notifier(&gpmc->nb);
2604 gpmc_free_irq(gpmc);
2605 gpmc_mem_exit();
2606 pm_runtime_put_sync(&pdev->dev);
2607 pm_runtime_disable(&pdev->dev);
2608
2609 return 0;
2610 }
2611
2612 #ifdef CONFIG_PM_SLEEP
gpmc_suspend(struct device * dev)2613 static int gpmc_suspend(struct device *dev)
2614 {
2615 struct gpmc_device *gpmc = dev_get_drvdata(dev);
2616
2617 omap3_gpmc_save_context(gpmc);
2618 pm_runtime_put_sync(dev);
2619 gpmc->is_suspended = 1;
2620
2621 return 0;
2622 }
2623
gpmc_resume(struct device * dev)2624 static int gpmc_resume(struct device *dev)
2625 {
2626 struct gpmc_device *gpmc = dev_get_drvdata(dev);
2627
2628 pm_runtime_get_sync(dev);
2629 omap3_gpmc_restore_context(gpmc);
2630 gpmc->is_suspended = 0;
2631
2632 return 0;
2633 }
2634 #endif
2635
2636 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2637
2638 #ifdef CONFIG_OF
2639 static const struct of_device_id gpmc_dt_ids[] = {
2640 { .compatible = "ti,omap2420-gpmc" },
2641 { .compatible = "ti,omap2430-gpmc" },
2642 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
2643 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
2644 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
2645 { .compatible = "ti,am64-gpmc" },
2646 { }
2647 };
2648 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
2649 #endif
2650
2651 static struct platform_driver gpmc_driver = {
2652 .probe = gpmc_probe,
2653 .remove = gpmc_remove,
2654 .driver = {
2655 .name = DEVICE_NAME,
2656 .of_match_table = of_match_ptr(gpmc_dt_ids),
2657 .pm = &gpmc_pm_ops,
2658 },
2659 };
2660
2661 module_platform_driver(gpmc_driver);
2662
2663 MODULE_DESCRIPTION("Texas Instruments GPMC driver");
2664 MODULE_LICENSE("GPL");
2665