Searched refs:GPLL0 (Results 1 – 25 of 70) sorted by relevance
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| /linux-6.1.9/Documentation/devicetree/bindings/interconnect/ |
| D | qcom,osm-l3.yaml | 55 #define GPLL0 165
62 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
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| /linux-6.1.9/Documentation/devicetree/bindings/clock/ |
| D | qcom,gpucc-sm8350.yaml | 27 - description: GPLL0 main branch source
28 - description: GPLL0 div branch source
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| D | qcom,gpucc-sdm660.yaml | 27 - description: GPLL0 main gpu branch
28 - description: GPLL0 divider gpu branch
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| D | qcom,qcm2290-dispcc.yaml | 26 - description: GPLL0 source from GCC
27 - description: GPLL0 div source from GCC
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| D | qcom,gpucc.yaml | 40 - description: GPLL0 main branch source
41 - description: GPLL0 div branch source
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| D | qcom,sdm845-dispcc.yaml | 28 - description: GPLL0 source from GCC
29 - description: GPLL0 div source from GCC
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| D | qcom,msm8998-gpucc.yaml | 25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
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| D | qcom,sm6115-dispcc.yaml | 30 - description: GPLL0 DISP DIV clock from GCC
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| D | qcom,sc7180-dispcc.yaml | 25 - description: GPLL0 source from GCC
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| D | qcom,dispcc-sm6350.yaml | 25 - description: GPLL0 source from GCC
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| /linux-6.1.9/include/dt-bindings/clock/ |
| D | qcom,gcc-mdm9607.h | 9 #define GPLL0 0 macro
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| D | qcom,gcc-sdx55.h | 10 #define GPLL0 3 macro
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| D | qcom,gcc-sdx65.h | 10 #define GPLL0 0 macro
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| D | qcom,gcc-sdm660.h | 111 #define GPLL0 101 macro
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| D | qcom,gcc-sc7180.h | 11 #define GPLL0 1 macro
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| D | qcom,gcc-msm8994.h | 11 #define GPLL0 1 macro
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| D | qcom,gcc-sm6350.h | 11 #define GPLL0 0 macro
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| D | qcom,gcc-msm8916.h | 9 #define GPLL0 0 macro
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| D | qcom,gcc-qcm2290.h | 10 #define GPLL0 0 macro
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| D | qcom,gcc-msm8909.h | 11 #define GPLL0 1 macro
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| D | qcom,gcc-sm6115.h | 10 #define GPLL0 0 macro
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| D | qcom,gcc-msm8939.h | 9 #define GPLL0 0 macro
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| D | qcom,gcc-msm8953.h | 183 #define GPLL0 176 macro
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| D | qcom,gcc-msm8976.h | 11 #define GPLL0 0 macro
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| /linux-6.1.9/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.yaml | 49 - description: GPLL0 Clock
196 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
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