Searched refs:GPCR (Results 1 – 12 of 12) sorted by relevance
178 GPCR = (BADGE4_GPIO_LGP2 | BADGE4_GPIO_LGP3 | in badge4_init()193 GPCR = (BADGE4_GPIO_SDSDA | BADGE4_GPIO_SDSCL); in badge4_init()197 GPCR = (BADGE4_GPIO_UART_HS1 | BADGE4_GPIO_UART_HS2); in badge4_init()201 GPCR = BADGE4_GPIO_MUXSEL0; in badge4_init()206 GPCR = BADGE4_GPIO_TESTPT_J7; in badge4_init()210 GPCR = BADGE4_GPIO_PCMEN5V; /* initially off */ in badge4_init()283 GPCR = BADGE4_GPIO_PCMEN5V; in badge4_set_5V()
126 GPCR = SDA; in adv7171_start()142 GPCR = SCK; in adv7171_send()147 GPCR = SDA; in adv7171_send()152 GPCR = SCK; in adv7171_send()162 GPCR = SCK | SDA; in adv7171_send()176 GPCR = SDA | SCK | MOD; /* clear L3 mode to ensure UDA1341 doesn't respond */ in adv7171_write()191 GPCR = (~gplr) & (SDA | SCK | MOD); in adv7171_write()563 GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM; in assabet_init()571 GPCR = GPIO_GPIO27; in assabet_init()
107 GPCR = ~gpio; in sa11x0_pm_enter()
133 GPCR = GPIO_ETH0_EN; /* clear MCLK (enable smc) */ in pleb_map_io()
112 GPCR = GPIO_GPIO25; in jornada_ssp_start()
440 GPCR = GPIO_MBGNT; in sa1110_mb_disable()459 GPCR = GPIO_MBGNT; in sa1110_mb_enable()
144 GPCR = SHANNON_GPIO_CODEC_RESET; in shannon_map_io()
269 GPCR = GPIO_GPIO20; /* stop gpio20 */ in jornada720_init()
285 GPCR = 0x0fffffff; /* All outputs are set low by default */ in h3xxx_map_io()
35 #define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24) macro375 GPCR(i * 32) = ~PGSR(i); in pxa2xx_mfp_suspend()399 GPCR(i * 32) = ~saved_gplr[i]; in pxa2xx_mfp_resume()
22 #define GPCR 0x04c /* pin clear w/o */ macro115 gpcr = gpio_reg(chip, offset, GPCR); in mrfld_gpio_set()
1108 #define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */ macro