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Searched refs:GCC_PCIE_0_BCR (Results 1 – 25 of 28) sorted by relevance

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/linux-6.1.9/include/dt-bindings/reset/
Dqcom,gcc-apq8084.h90 #define GCC_PCIE_0_BCR 81 macro
/linux-6.1.9/include/dt-bindings/clock/
Dqcom,gcc-sm6350.h165 #define GCC_PCIE_0_BCR 6 macro
Dqcom,gcc-qcs404.h165 #define GCC_PCIE_0_BCR 9 macro
Dqcom,gcc-sc7280.h209 #define GCC_PCIE_0_BCR 0 macro
Dqcom,gcc-sm8450.h204 #define GCC_PCIE_0_BCR 4 macro
Dqcom,gcc-sdm845.h206 #define GCC_PCIE_0_BCR 1 macro
Dqcom,gcc-sm8150.h217 #define GCC_PCIE_0_BCR 4 macro
Dqcom,gcc-sm8250.h216 #define GCC_PCIE_0_BCR 4 macro
Dqcom,gcc-sm8350.h219 #define GCC_PCIE_0_BCR 4 macro
Dqcom,gcc-msm8998.h210 #define GCC_PCIE_0_BCR 12 macro
Dqcom,gcc-sc8180x.h254 #define GCC_PCIE_0_BCR 4 macro
Dqcom,gcc-msm8996.h319 #define GCC_PCIE_0_BCR 79 macro
/linux-6.1.9/arch/arm64/boot/dts/qcom/
Dqcs404.dtsi1329 <&gcc GCC_PCIE_0_BCR>,
Dsm8450.dtsi1770 resets = <&gcc GCC_PCIE_0_BCR>;
/linux-6.1.9/drivers/clk/qcom/
Dgcc-qcs404.c2794 [GCC_PCIE_0_BCR] = { 0x3e000 },
Dgcc-sm8450.c3135 [GCC_PCIE_0_BCR] = { 0x7b000 },
Dgcc-msm8998.c3116 [GCC_PCIE_0_BCR] = { 0x6b000 },
Dgcc-apq8084.c3562 [GCC_PCIE_0_BCR] = { 0x1ac0 },
Dgcc-sc7280.c3388 [GCC_PCIE_0_BCR] = { 0x6b000 },
Dgcc-sm8250.c3541 [GCC_PCIE_0_BCR] = { 0x6b000 },
Dgcc-sm8150.c3734 [GCC_PCIE_0_BCR] = { 0x6b000 },
Dgcc-sm8350.c3751 [GCC_PCIE_0_BCR] = { 0x6b000 },
Dgcc-msm8996.c3783 [GCC_PCIE_0_BCR] = { 0x6b000 },
Dgcc-sdm845.c3875 [GCC_PCIE_0_BCR] = { 0x6b000 },
Dgcc-sc8180x.c4494 [GCC_PCIE_0_BCR] = { 0x6b000 },

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