Searched refs:EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG (Results 1 – 3 of 3) sorted by relevance
82 { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
98 { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
425 #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260 macro