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Searched refs:EXC (Results 1 – 10 of 10) sorted by relevance

/linux-6.1.9/arch/mips/cavium-octeon/
Docteon-memcpy.S74 #define EXC(inst_reg,addr,handler) \ macro
187 EXC( LOAD t0, UNIT(0)(src), l_exc)
188 EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
189 EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
190 EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
192 EXC( STORE t0, UNIT(0)(dst), s_exc_p16u)
193 EXC( STORE t1, UNIT(1)(dst), s_exc_p15u)
194 EXC( STORE t2, UNIT(2)(dst), s_exc_p14u)
195 EXC( STORE t3, UNIT(3)(dst), s_exc_p13u)
196 EXC( LOAD t0, UNIT(4)(src), l_exc_copy)
[all …]
/linux-6.1.9/arch/alpha/kernel/
Dtraps.c459 EXC(1b,3b,%1,%0) in do_entUna()
460 EXC(2b,3b,%2,%0) in do_entUna()
475 EXC(1b,3b,%1,%0) in do_entUna()
476 EXC(2b,3b,%2,%0) in do_entUna()
491 EXC(1b,3b,%1,%0) in do_entUna()
492 EXC(2b,3b,%2,%0) in do_entUna()
516 EXC(1b,5b,%2,%0) in do_entUna()
517 EXC(2b,5b,%1,%0) in do_entUna()
518 EXC(3b,5b,$31,%0) in do_entUna()
519 EXC(4b,5b,$31,%0) in do_entUna()
[all …]
/linux-6.1.9/arch/sh/lib/
Dchecksum.S184 #define EXC(...) \ macro
226 EXC( mov.b @r4+,r1 )
227 EXC( mov.b @r4+,r0 )
229 EXC( mov.b r1,@r5 )
230 EXC( mov.b r0,@(1,r5) )
259 EXC( mov.w @r4+,r0 )
260 EXC( mov.w r0,@r5 )
275 EXC( mov.l @r4+,r0 )
276 EXC( mov.l @r4+,r1 )
278 EXC( mov.l r0,@r5 )
[all …]
/linux-6.1.9/arch/alpha/include/asm/
Duaccess.h39 #define EXC(label,cont,res,err) \ macro
88 EXC(1b,2b,%0,%1) \
95 EXC(1b,2b,%0,%1) \
105 EXC(1b,2b,%0,%1) \
112 EXC(1b,2b,%0,%1) \
128 EXC(1b,3b,%0,%2) \
129 EXC(2b,3b,%0,%2) \
138 EXC(1b,2b,%0,%1) \
184 EXC(1b,2b,$31,%0) \
191 EXC(1b,2b,$31,%0) \
[all …]
Dfutex.h23 EXC(1b,3b,$31,%1) \
24 EXC(2b,3b,$31,%1) \
84 EXC(1b,3b,$31,%0) in futex_atomic_cmpxchg_inatomic()
85 EXC(2b,3b,$31,%0) in futex_atomic_cmpxchg_inatomic()
/linux-6.1.9/arch/mips/lib/
Dmemcpy.S115 #define EXC(insn, type, reg, addr, handler) \ macro
149 #define LOAD(reg, addr, handler) EXC(ld, LD_INSN, reg, addr, handler)
150 #define LOADL(reg, addr, handler) EXC(ldl, LD_INSN, reg, addr, handler)
151 #define LOADR(reg, addr, handler) EXC(ldr, LD_INSN, reg, addr, handler)
152 #define STOREL(reg, addr, handler) EXC(sdl, ST_INSN, reg, addr, handler)
153 #define STORER(reg, addr, handler) EXC(sdr, ST_INSN, reg, addr, handler)
154 #define STORE(reg, addr, handler) EXC(sd, ST_INSN, reg, addr, handler)
186 #define LOAD(reg, addr, handler) EXC(lw, LD_INSN, reg, addr, handler)
187 #define LOADL(reg, addr, handler) EXC(lwl, LD_INSN, reg, addr, handler)
188 #define LOADR(reg, addr, handler) EXC(lwr, LD_INSN, reg, addr, handler)
[all …]
Dcsum_partial.S346 #define EXC(insn, type, reg, addr) \ macro
372 #define LOAD(reg, addr) EXC(ld, LD_INSN, reg, addr)
373 #define LOADBU(reg, addr) EXC(lbu, LD_INSN, reg, addr)
374 #define LOADL(reg, addr) EXC(ldl, LD_INSN, reg, addr)
375 #define LOADR(reg, addr) EXC(ldr, LD_INSN, reg, addr)
376 #define STOREB(reg, addr) EXC(sb, ST_INSN, reg, addr)
377 #define STOREL(reg, addr) EXC(sdl, ST_INSN, reg, addr)
378 #define STORER(reg, addr) EXC(sdr, ST_INSN, reg, addr)
379 #define STORE(reg, addr) EXC(sd, ST_INSN, reg, addr)
392 #define LOAD(reg, addr) EXC(lw, LD_INSN, reg, addr)
[all …]
/linux-6.1.9/arch/x86/lib/
Dchecksum_32.S263 #define EXC(y...) \ macro
288 EXC(1: movw (%esi), %bx )
290 EXC( movw %bx, (%edi) )
/linux-6.1.9/arch/alpha/lib/
Dcsum_partial_copy.c49 EXC(1b,2b,%0,%1) \
/linux-6.1.9/arch/m68k/ifpsp060/src/
Dfpsp.S16162 # then, the SNAN bit is set in the FPSR EXC byte. If the SNAN trap #