1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* $Id: sunhme.h,v 1.33 2001/08/03 06:23:04 davem Exp $
3  * sunhme.h: Definitions for Sparc HME/BigMac 10/100baseT ethernet driver.
4  *           Also known as the "Happy Meal".
5  *
6  * Copyright (C) 1996, 1999 David S. Miller (davem@redhat.com)
7  */
8 
9 #ifndef _SUNHME_H
10 #define _SUNHME_H
11 
12 #include <linux/pci.h>
13 
14 /* Happy Meal global registers. */
15 #define GREG_SWRESET	0x000UL	/* Software Reset  */
16 #define GREG_CFG	0x004UL	/* Config Register */
17 #define GREG_STAT	0x100UL	/* Status          */
18 #define GREG_IMASK	0x104UL	/* Interrupt Mask  */
19 #define GREG_REG_SIZE	0x108UL
20 
21 /* Global reset register. */
22 #define GREG_RESET_ETX         0x01
23 #define GREG_RESET_ERX         0x02
24 #define GREG_RESET_ALL         0x03
25 
26 /* Global config register. */
27 #define GREG_CFG_BURSTMSK      0x03
28 #define GREG_CFG_BURST16       0x00
29 #define GREG_CFG_BURST32       0x01
30 #define GREG_CFG_BURST64       0x02
31 #define GREG_CFG_64BIT         0x04
32 #define GREG_CFG_PARITY        0x08
33 #define GREG_CFG_RESV          0x10
34 
35 /* Global status register. */
36 #define GREG_STAT_GOTFRAME     0x00000001 /* Received a frame                         */
37 #define GREG_STAT_RCNTEXP      0x00000002 /* Receive frame counter expired            */
38 #define GREG_STAT_ACNTEXP      0x00000004 /* Align-error counter expired              */
39 #define GREG_STAT_CCNTEXP      0x00000008 /* CRC-error counter expired                */
40 #define GREG_STAT_LCNTEXP      0x00000010 /* Length-error counter expired             */
41 #define GREG_STAT_RFIFOVF      0x00000020 /* Receive FIFO overflow                    */
42 #define GREG_STAT_CVCNTEXP     0x00000040 /* Code-violation counter expired           */
43 #define GREG_STAT_STSTERR      0x00000080 /* Test error in XIF for SQE                */
44 #define GREG_STAT_SENTFRAME    0x00000100 /* Transmitted a frame                      */
45 #define GREG_STAT_TFIFO_UND    0x00000200 /* Transmit FIFO underrun                   */
46 #define GREG_STAT_MAXPKTERR    0x00000400 /* Max-packet size error                    */
47 #define GREG_STAT_NCNTEXP      0x00000800 /* Normal-collision counter expired         */
48 #define GREG_STAT_ECNTEXP      0x00001000 /* Excess-collision counter expired         */
49 #define GREG_STAT_LCCNTEXP     0x00002000 /* Late-collision counter expired           */
50 #define GREG_STAT_FCNTEXP      0x00004000 /* First-collision counter expired          */
51 #define GREG_STAT_DTIMEXP      0x00008000 /* Defer-timer expired                      */
52 #define GREG_STAT_RXTOHOST     0x00010000 /* Moved from receive-FIFO to host memory   */
53 #define GREG_STAT_NORXD        0x00020000 /* No more receive descriptors              */
54 #define GREG_STAT_RXERR        0x00040000 /* Error during receive dma                 */
55 #define GREG_STAT_RXLATERR     0x00080000 /* Late error during receive dma            */
56 #define GREG_STAT_RXPERR       0x00100000 /* Parity error during receive dma          */
57 #define GREG_STAT_RXTERR       0x00200000 /* Tag error during receive dma             */
58 #define GREG_STAT_EOPERR       0x00400000 /* Transmit descriptor did not have EOP set */
59 #define GREG_STAT_MIFIRQ       0x00800000 /* MIF is signaling an interrupt condition  */
60 #define GREG_STAT_HOSTTOTX     0x01000000 /* Moved from host memory to transmit-FIFO  */
61 #define GREG_STAT_TXALL        0x02000000 /* Transmitted all packets in the tx-fifo   */
62 #define GREG_STAT_TXEACK       0x04000000 /* Error during transmit dma                */
63 #define GREG_STAT_TXLERR       0x08000000 /* Late error during transmit dma           */
64 #define GREG_STAT_TXPERR       0x10000000 /* Parity error during transmit dma         */
65 #define GREG_STAT_TXTERR       0x20000000 /* Tag error during transmit dma            */
66 #define GREG_STAT_SLVERR       0x40000000 /* PIO access got an error                  */
67 #define GREG_STAT_SLVPERR      0x80000000 /* PIO access got a parity error            */
68 
69 /* All interesting error conditions. */
70 #define GREG_STAT_ERRORS       0xfc7efefc
71 
72 /* Global interrupt mask register. */
73 #define GREG_IMASK_GOTFRAME    0x00000001 /* Received a frame                         */
74 #define GREG_IMASK_RCNTEXP     0x00000002 /* Receive frame counter expired            */
75 #define GREG_IMASK_ACNTEXP     0x00000004 /* Align-error counter expired              */
76 #define GREG_IMASK_CCNTEXP     0x00000008 /* CRC-error counter expired                */
77 #define GREG_IMASK_LCNTEXP     0x00000010 /* Length-error counter expired             */
78 #define GREG_IMASK_RFIFOVF     0x00000020 /* Receive FIFO overflow                    */
79 #define GREG_IMASK_CVCNTEXP    0x00000040 /* Code-violation counter expired           */
80 #define GREG_IMASK_STSTERR     0x00000080 /* Test error in XIF for SQE                */
81 #define GREG_IMASK_SENTFRAME   0x00000100 /* Transmitted a frame                      */
82 #define GREG_IMASK_TFIFO_UND   0x00000200 /* Transmit FIFO underrun                   */
83 #define GREG_IMASK_MAXPKTERR   0x00000400 /* Max-packet size error                    */
84 #define GREG_IMASK_NCNTEXP     0x00000800 /* Normal-collision counter expired         */
85 #define GREG_IMASK_ECNTEXP     0x00001000 /* Excess-collision counter expired         */
86 #define GREG_IMASK_LCCNTEXP    0x00002000 /* Late-collision counter expired           */
87 #define GREG_IMASK_FCNTEXP     0x00004000 /* First-collision counter expired          */
88 #define GREG_IMASK_DTIMEXP     0x00008000 /* Defer-timer expired                      */
89 #define GREG_IMASK_RXTOHOST    0x00010000 /* Moved from receive-FIFO to host memory   */
90 #define GREG_IMASK_NORXD       0x00020000 /* No more receive descriptors              */
91 #define GREG_IMASK_RXERR       0x00040000 /* Error during receive dma                 */
92 #define GREG_IMASK_RXLATERR    0x00080000 /* Late error during receive dma            */
93 #define GREG_IMASK_RXPERR      0x00100000 /* Parity error during receive dma          */
94 #define GREG_IMASK_RXTERR      0x00200000 /* Tag error during receive dma             */
95 #define GREG_IMASK_EOPERR      0x00400000 /* Transmit descriptor did not have EOP set */
96 #define GREG_IMASK_MIFIRQ      0x00800000 /* MIF is signaling an interrupt condition  */
97 #define GREG_IMASK_HOSTTOTX    0x01000000 /* Moved from host memory to transmit-FIFO  */
98 #define GREG_IMASK_TXALL       0x02000000 /* Transmitted all packets in the tx-fifo   */
99 #define GREG_IMASK_TXEACK      0x04000000 /* Error during transmit dma                */
100 #define GREG_IMASK_TXLERR      0x08000000 /* Late error during transmit dma           */
101 #define GREG_IMASK_TXPERR      0x10000000 /* Parity error during transmit dma         */
102 #define GREG_IMASK_TXTERR      0x20000000 /* Tag error during transmit dma            */
103 #define GREG_IMASK_SLVERR      0x40000000 /* PIO access got an error                  */
104 #define GREG_IMASK_SLVPERR     0x80000000 /* PIO access got a parity error            */
105 
106 /* Happy Meal external transmitter registers. */
107 #define ETX_PENDING	0x00UL	/* Transmit pending/wakeup register */
108 #define ETX_CFG		0x04UL	/* Transmit config register         */
109 #define ETX_RING	0x08UL	/* Transmit ring pointer            */
110 #define ETX_BBASE	0x0cUL	/* Transmit buffer base             */
111 #define ETX_BDISP	0x10UL	/* Transmit buffer displacement     */
112 #define ETX_FIFOWPTR	0x14UL	/* FIFO write ptr                   */
113 #define ETX_FIFOSWPTR	0x18UL	/* FIFO write ptr (shadow register) */
114 #define ETX_FIFORPTR	0x1cUL	/* FIFO read ptr                    */
115 #define ETX_FIFOSRPTR	0x20UL	/* FIFO read ptr (shadow register)  */
116 #define ETX_FIFOPCNT	0x24UL	/* FIFO packet counter              */
117 #define ETX_SMACHINE	0x28UL	/* Transmitter state machine        */
118 #define ETX_RSIZE	0x2cUL	/* Ring descriptor size             */
119 #define ETX_BPTR	0x30UL	/* Transmit data buffer ptr         */
120 #define ETX_REG_SIZE	0x34UL
121 
122 /* ETX transmit pending register. */
123 #define ETX_TP_DMAWAKEUP         0x00000001 /* Restart transmit dma             */
124 
125 /* ETX config register. */
126 #define ETX_CFG_DMAENABLE        0x00000001 /* Enable transmit dma              */
127 #define ETX_CFG_FIFOTHRESH       0x000003fe /* Transmit FIFO threshold          */
128 #define ETX_CFG_IRQDAFTER        0x00000400 /* Interrupt after TX-FIFO drained  */
129 #define ETX_CFG_IRQDBEFORE       0x00000000 /* Interrupt before TX-FIFO drained */
130 
131 #define ETX_RSIZE_SHIFT          4
132 
133 /* Happy Meal external receiver registers. */
134 #define ERX_CFG		0x00UL	/* Receiver config register         */
135 #define ERX_RING	0x04UL	/* Receiver ring ptr                */
136 #define ERX_BPTR	0x08UL	/* Receiver buffer ptr              */
137 #define ERX_FIFOWPTR	0x0cUL	/* FIFO write ptr                   */
138 #define ERX_FIFOSWPTR	0x10UL	/* FIFO write ptr (shadow register) */
139 #define ERX_FIFORPTR	0x14UL	/* FIFO read ptr                    */
140 #define ERX_FIFOSRPTR	0x18UL	/* FIFO read ptr (shadow register)  */
141 #define ERX_SMACHINE	0x1cUL	/* Receiver state machine           */
142 #define ERX_REG_SIZE	0x20UL
143 
144 /* ERX config register. */
145 #define ERX_CFG_DMAENABLE    0x00000001 /* Enable receive DMA        */
146 #define ERX_CFG_RESV1        0x00000006 /* Unused...                 */
147 #define ERX_CFG_BYTEOFFSET   0x00000038 /* Receive first byte offset */
148 #define ERX_CFG_RESV2        0x000001c0 /* Unused...                 */
149 #define ERX_CFG_SIZE32       0x00000000 /* Receive ring size == 32   */
150 #define ERX_CFG_SIZE64       0x00000200 /* Receive ring size == 64   */
151 #define ERX_CFG_SIZE128      0x00000400 /* Receive ring size == 128  */
152 #define ERX_CFG_SIZE256      0x00000600 /* Receive ring size == 256  */
153 #define ERX_CFG_RESV3        0x0000f800 /* Unused...                 */
154 #define ERX_CFG_CSUMSTART    0x007f0000 /* Offset of checksum start,
155 					 * in halfwords. */
156 
157 /* I'd like a Big Mac, small fries, small coke, and SparcLinux please. */
158 #define BMAC_XIFCFG	0x0000UL	/* XIF config register                */
159 	/* 0x4-->0x204, reserved */
160 #define BMAC_TXSWRESET	0x208UL	/* Transmitter software reset         */
161 #define BMAC_TXCFG	0x20cUL	/* Transmitter config register        */
162 #define BMAC_IGAP1	0x210UL	/* Inter-packet gap 1                 */
163 #define BMAC_IGAP2	0x214UL	/* Inter-packet gap 2                 */
164 #define BMAC_ALIMIT	0x218UL	/* Transmit attempt limit             */
165 #define BMAC_STIME	0x21cUL	/* Transmit slot time                 */
166 #define BMAC_PLEN	0x220UL	/* Size of transmit preamble          */
167 #define BMAC_PPAT	0x224UL	/* Pattern for transmit preamble      */
168 #define BMAC_TXSDELIM	0x228UL	/* Transmit delimiter                 */
169 #define BMAC_JSIZE	0x22cUL	/* Jam size                           */
170 #define BMAC_TXMAX	0x230UL	/* Transmit max pkt size              */
171 #define BMAC_TXMIN	0x234UL	/* Transmit min pkt size              */
172 #define BMAC_PATTEMPT	0x238UL	/* Count of transmit peak attempts    */
173 #define BMAC_DTCTR	0x23cUL	/* Transmit defer timer               */
174 #define BMAC_NCCTR	0x240UL	/* Transmit normal-collision counter  */
175 #define BMAC_FCCTR	0x244UL	/* Transmit first-collision counter   */
176 #define BMAC_EXCTR	0x248UL	/* Transmit excess-collision counter  */
177 #define BMAC_LTCTR	0x24cUL	/* Transmit late-collision counter    */
178 #define BMAC_RSEED	0x250UL	/* Transmit random number seed        */
179 #define BMAC_TXSMACHINE	0x254UL	/* Transmit state machine             */
180 	/* 0x258-->0x304, reserved */
181 #define BMAC_RXSWRESET	0x308UL	/* Receiver software reset            */
182 #define BMAC_RXCFG	0x30cUL	/* Receiver config register           */
183 #define BMAC_RXMAX	0x310UL	/* Receive max pkt size               */
184 #define BMAC_RXMIN	0x314UL	/* Receive min pkt size               */
185 #define BMAC_MACADDR2	0x318UL	/* Ether address register 2           */
186 #define BMAC_MACADDR1	0x31cUL	/* Ether address register 1           */
187 #define BMAC_MACADDR0	0x320UL	/* Ether address register 0           */
188 #define BMAC_FRCTR	0x324UL	/* Receive frame receive counter      */
189 #define BMAC_GLECTR	0x328UL	/* Receive giant-length error counter */
190 #define BMAC_UNALECTR	0x32cUL	/* Receive unaligned error counter    */
191 #define BMAC_RCRCECTR	0x330UL	/* Receive CRC error counter          */
192 #define BMAC_RXSMACHINE	0x334UL	/* Receiver state machine             */
193 #define BMAC_RXCVALID	0x338UL	/* Receiver code violation            */
194 	/* 0x33c, reserved */
195 #define BMAC_HTABLE3	0x340UL	/* Hash table 3                       */
196 #define BMAC_HTABLE2	0x344UL	/* Hash table 2                       */
197 #define BMAC_HTABLE1	0x348UL	/* Hash table 1                       */
198 #define BMAC_HTABLE0	0x34cUL	/* Hash table 0                       */
199 #define BMAC_AFILTER2	0x350UL	/* Address filter 2                   */
200 #define BMAC_AFILTER1	0x354UL	/* Address filter 1                   */
201 #define BMAC_AFILTER0	0x358UL	/* Address filter 0                   */
202 #define BMAC_AFMASK	0x35cUL	/* Address filter mask                */
203 #define BMAC_REG_SIZE	0x360UL
204 
205 /* BigMac XIF config register. */
206 #define BIGMAC_XCFG_ODENABLE  0x00000001 /* Output driver enable         */
207 #define BIGMAC_XCFG_XLBACK    0x00000002 /* Loopback-mode XIF enable     */
208 #define BIGMAC_XCFG_MLBACK    0x00000004 /* Loopback-mode MII enable     */
209 #define BIGMAC_XCFG_MIIDISAB  0x00000008 /* MII receive buffer disable   */
210 #define BIGMAC_XCFG_SQENABLE  0x00000010 /* SQE test enable              */
211 #define BIGMAC_XCFG_SQETWIN   0x000003e0 /* SQE time window              */
212 #define BIGMAC_XCFG_LANCE     0x00000010 /* Lance mode enable            */
213 #define BIGMAC_XCFG_LIPG0     0x000003e0 /* Lance mode IPG0              */
214 
215 /* BigMac transmit config register. */
216 #define BIGMAC_TXCFG_ENABLE   0x00000001 /* Enable the transmitter       */
217 #define BIGMAC_TXCFG_SMODE    0x00000020 /* Enable slow transmit mode    */
218 #define BIGMAC_TXCFG_CIGN     0x00000040 /* Ignore transmit collisions   */
219 #define BIGMAC_TXCFG_FCSOFF   0x00000080 /* Do not emit FCS              */
220 #define BIGMAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff              */
221 #define BIGMAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex           */
222 #define BIGMAC_TXCFG_DGIVEUP  0x00000400 /* Don't give up on transmits   */
223 
224 /* BigMac receive config register. */
225 #define BIGMAC_RXCFG_ENABLE   0x00000001 /* Enable the receiver             */
226 #define BIGMAC_RXCFG_PSTRIP   0x00000020 /* Pad byte strip enable           */
227 #define BIGMAC_RXCFG_PMISC    0x00000040 /* Enable promiscuous mode          */
228 #define BIGMAC_RXCFG_DERR     0x00000080 /* Disable error checking          */
229 #define BIGMAC_RXCFG_DCRCS    0x00000100 /* Disable CRC stripping           */
230 #define BIGMAC_RXCFG_REJME    0x00000200 /* Reject packets addressed to me  */
231 #define BIGMAC_RXCFG_PGRP     0x00000400 /* Enable promisc group mode       */
232 #define BIGMAC_RXCFG_HENABLE  0x00000800 /* Enable the hash filter          */
233 #define BIGMAC_RXCFG_AENABLE  0x00001000 /* Enable the address filter       */
234 
235 /* These are the "Management Interface" (ie. MIF) registers of the transceiver. */
236 #define TCVR_BBCLOCK	0x00UL	/* Bit bang clock register          */
237 #define TCVR_BBDATA	0x04UL	/* Bit bang data register           */
238 #define TCVR_BBOENAB	0x08UL	/* Bit bang output enable           */
239 #define TCVR_FRAME	0x0cUL	/* Frame control/data register      */
240 #define TCVR_CFG	0x10UL	/* MIF config register              */
241 #define TCVR_IMASK	0x14UL	/* MIF interrupt mask               */
242 #define TCVR_STATUS	0x18UL	/* MIF status                       */
243 #define TCVR_SMACHINE	0x1cUL	/* MIF state machine                */
244 #define TCVR_REG_SIZE	0x20UL
245 
246 /* Frame commands. */
247 #define FRAME_WRITE           0x50020000
248 #define FRAME_READ            0x60020000
249 
250 /* Transceiver config register */
251 #define TCV_CFG_PSELECT       0x00000001 /* Select PHY                      */
252 #define TCV_CFG_PENABLE       0x00000002 /* Enable MIF polling              */
253 #define TCV_CFG_BENABLE       0x00000004 /* Enable the "bit banger" oh baby */
254 #define TCV_CFG_PREGADDR      0x000000f8 /* Address of poll register        */
255 #define TCV_CFG_MDIO0         0x00000100 /* MDIO zero, data/attached        */
256 #define TCV_CFG_MDIO1         0x00000200 /* MDIO one,  data/attached        */
257 #define TCV_CFG_PDADDR        0x00007c00 /* Device PHY address polling      */
258 
259 /* Here are some PHY addresses. */
260 #define TCV_PADDR_ETX         0          /* Internal transceiver            */
261 #define TCV_PADDR_ITX         1          /* External transceiver            */
262 
263 /* Transceiver status register */
264 #define TCV_STAT_BASIC        0xffff0000 /* The "basic" part                */
265 #define TCV_STAT_NORMAL       0x0000ffff /* The "non-basic" part            */
266 
267 /* Inside the Happy Meal transceiver is the physical layer, they use an
268  * implementations for National Semiconductor, part number DP83840VCE.
269  * You can retrieve the data sheets and programming docs for this beast
270  * from http://www.national.com/
271  *
272  * The DP83840 is capable of both 10 and 100Mbps ethernet, in both
273  * half and full duplex mode.  It also supports auto negotiation.
274  *
275  * But.... THIS THING IS A PAIN IN THE ASS TO PROGRAM!
276  * Debugging eeprom burnt code is more fun than programming this chip!
277  */
278 
279 /* Generic MII registers defined in linux/mii.h, these below
280  * are DP83840 specific.
281  */
282 #define DP83840_CSCONFIG        0x17        /* CS configuration            */
283 
284 /* The Carrier Sense config register. */
285 #define CSCONFIG_RESV1          0x0001  /* Unused...                   */
286 #define CSCONFIG_LED4           0x0002  /* Pin for full-dplx LED4      */
287 #define CSCONFIG_LED1           0x0004  /* Pin for conn-status LED1    */
288 #define CSCONFIG_RESV2          0x0008  /* Unused...                   */
289 #define CSCONFIG_TCVDISAB       0x0010  /* Turns off the transceiver   */
290 #define CSCONFIG_DFBYPASS       0x0020  /* Bypass disconnect function  */
291 #define CSCONFIG_GLFORCE        0x0040  /* Good link force for 100mbps */
292 #define CSCONFIG_CLKTRISTATE    0x0080  /* Tristate 25m clock          */
293 #define CSCONFIG_RESV3          0x0700  /* Unused...                   */
294 #define CSCONFIG_ENCODE         0x0800  /* 1=MLT-3, 0=binary           */
295 #define CSCONFIG_RENABLE        0x1000  /* Repeater mode enable        */
296 #define CSCONFIG_TCDISABLE      0x2000  /* Disable timeout counter     */
297 #define CSCONFIG_RESV4          0x4000  /* Unused...                   */
298 #define CSCONFIG_NDISABLE       0x8000  /* Disable NRZI                */
299 
300 /* Happy Meal descriptor rings and such.
301  * All descriptor rings must be aligned on a 2K boundary.
302  * All receive buffers must be 64 byte aligned.
303  * Always write the address first before setting the ownership
304  * bits to avoid races with the hardware scanning the ring.
305  */
306 typedef u32 __bitwise hme32;
307 
308 struct happy_meal_rxd {
309 	hme32 rx_flags;
310 	hme32 rx_addr;
311 };
312 
313 #define RXFLAG_OWN         0x80000000 /* 1 = hardware, 0 = software */
314 #define RXFLAG_OVERFLOW    0x40000000 /* 1 = buffer overflow        */
315 #define RXFLAG_SIZE        0x3fff0000 /* Size of the buffer         */
316 #define RXFLAG_CSUM        0x0000ffff /* HW computed checksum       */
317 
318 struct happy_meal_txd {
319 	hme32 tx_flags;
320 	hme32 tx_addr;
321 };
322 
323 #define TXFLAG_OWN         0x80000000 /* 1 = hardware, 0 = software */
324 #define TXFLAG_SOP         0x40000000 /* 1 = start of packet        */
325 #define TXFLAG_EOP         0x20000000 /* 1 = end of packet          */
326 #define TXFLAG_CSENABLE    0x10000000 /* 1 = enable hw-checksums    */
327 #define TXFLAG_CSLOCATION  0x0ff00000 /* Where to stick the csum    */
328 #define TXFLAG_CSBUFBEGIN  0x000fc000 /* Where to begin checksum    */
329 #define TXFLAG_SIZE        0x00003fff /* Size of the packet         */
330 
331 #define TX_RING_SIZE       32         /* Must be >16 and <255, multiple of 16  */
332 #define RX_RING_SIZE       32         /* see ERX_CFG_SIZE* for possible values */
333 
334 #if (TX_RING_SIZE < 16 || TX_RING_SIZE > 256 || (TX_RING_SIZE % 16) != 0)
335 #error TX_RING_SIZE holds illegal value
336 #endif
337 
338 #define TX_RING_MAXSIZE    256
339 #define RX_RING_MAXSIZE    256
340 
341 /* We use a 14 byte offset for checksum computation. */
342 #if (RX_RING_SIZE == 32)
343 #define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE32|((14/2)<<16))
344 #else
345 #if (RX_RING_SIZE == 64)
346 #define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE64|((14/2)<<16))
347 #else
348 #if (RX_RING_SIZE == 128)
349 #define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE128|((14/2)<<16))
350 #else
351 #if (RX_RING_SIZE == 256)
352 #define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE256|((14/2)<<16))
353 #else
354 #error RX_RING_SIZE holds illegal value
355 #endif
356 #endif
357 #endif
358 #endif
359 
360 #define NEXT_RX(num)       (((num) + 1) & (RX_RING_SIZE - 1))
361 #define NEXT_TX(num)       (((num) + 1) & (TX_RING_SIZE - 1))
362 #define PREV_RX(num)       (((num) - 1) & (RX_RING_SIZE - 1))
363 #define PREV_TX(num)       (((num) - 1) & (TX_RING_SIZE - 1))
364 
365 #define TX_BUFFS_AVAIL(hp)                                    \
366         (((hp)->tx_old <= (hp)->tx_new) ?                     \
367 	  (hp)->tx_old + (TX_RING_SIZE - 1) - (hp)->tx_new :  \
368 			    (hp)->tx_old - (hp)->tx_new - 1)
369 
370 #define RX_OFFSET          2
371 #define RX_BUF_ALLOC_SIZE  (1546 + RX_OFFSET + 64)
372 
373 #define RX_COPY_THRESHOLD  256
374 
375 struct hmeal_init_block {
376 	struct happy_meal_rxd happy_meal_rxd[RX_RING_MAXSIZE];
377 	struct happy_meal_txd happy_meal_txd[TX_RING_MAXSIZE];
378 };
379 
380 #define hblock_offset(mem, elem) \
381 ((__u32)((unsigned long)(&(((struct hmeal_init_block *)0)->mem[elem]))))
382 
383 /* Now software state stuff. */
384 enum happy_transceiver {
385 	external = 0,
386 	internal = 1,
387 	none     = 2,
388 };
389 
390 /* Timer state engine. */
391 enum happy_timer_state {
392 	arbwait  = 0,  /* Waiting for auto negotiation to complete.          */
393 	lupwait  = 1,  /* Auto-neg complete, awaiting link-up status.        */
394 	ltrywait = 2,  /* Forcing try of all modes, from fastest to slowest. */
395 	asleep   = 3,  /* Time inactive.                                     */
396 };
397 
398 struct quattro;
399 
400 /* Happy happy, joy joy! */
401 struct happy_meal {
402 	void __iomem	*gregs;			/* Happy meal global registers       */
403 	struct hmeal_init_block  *happy_block;	/* RX and TX descriptors (CPU addr)  */
404 
405 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
406 	u32 (*read_desc32)(hme32 *);
407 	void (*write_txd)(struct happy_meal_txd *, u32, u32);
408 	void (*write_rxd)(struct happy_meal_rxd *, u32, u32);
409 #endif
410 
411 	/* This is either an platform_device or a pci_dev. */
412 	void			  *happy_dev;
413 	struct device		  *dma_dev;
414 
415 	spinlock_t		  happy_lock;
416 
417 	struct sk_buff           *rx_skbs[RX_RING_SIZE];
418 	struct sk_buff           *tx_skbs[TX_RING_SIZE];
419 
420 	int rx_new, tx_new, rx_old, tx_old;
421 
422 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
423 	u32 (*read32)(void __iomem *);
424 	void (*write32)(void __iomem *, u32);
425 #endif
426 
427 	void __iomem	*etxregs;        /* External transmitter regs        */
428 	void __iomem	*erxregs;        /* External receiver regs           */
429 	void __iomem	*bigmacregs;     /* BIGMAC core regs		     */
430 	void __iomem	*tcvregs;        /* MIF transceiver regs             */
431 
432 	dma_addr_t                hblock_dvma;    /* DVMA visible address happy block  */
433 	unsigned int              happy_flags;    /* Driver state flags                */
434 	int                       irq;
435 	enum happy_transceiver    tcvr_type;      /* Kind of transceiver in use        */
436 	unsigned int              happy_bursts;   /* Get your mind out of the gutter   */
437 	unsigned int              paddr;          /* PHY address for transceiver       */
438 	unsigned short            hm_revision;    /* Happy meal revision               */
439 	unsigned short            sw_bmcr;        /* SW copy of BMCR                   */
440 	unsigned short            sw_bmsr;        /* SW copy of BMSR                   */
441 	unsigned short            sw_physid1;     /* SW copy of PHYSID1                */
442 	unsigned short            sw_physid2;     /* SW copy of PHYSID2                */
443 	unsigned short            sw_advertise;   /* SW copy of ADVERTISE              */
444 	unsigned short            sw_lpa;         /* SW copy of LPA                    */
445 	unsigned short            sw_expansion;   /* SW copy of EXPANSION              */
446 	unsigned short            sw_csconfig;    /* SW copy of CSCONFIG               */
447 	unsigned int              auto_speed;     /* Auto-nego link speed              */
448         unsigned int              forced_speed;   /* Force mode link speed             */
449 	unsigned int              poll_data;      /* MIF poll data                     */
450 	unsigned int              poll_flag;      /* MIF poll flag                     */
451 	unsigned int              linkcheck;      /* Have we checked the link yet?     */
452 	unsigned int              lnkup;          /* Is the link up as far as we know? */
453 	unsigned int              lnkdown;        /* Trying to force the link down?    */
454 	unsigned int              lnkcnt;         /* Counter for link-up attempts.     */
455 	struct timer_list         happy_timer;    /* To watch the link when coming up. */
456 	enum happy_timer_state    timer_state;    /* State of the auto-neg timer.      */
457 	unsigned int              timer_ticks;    /* Number of clicks at each state.   */
458 
459 	struct net_device	 *dev;		/* Backpointer                       */
460 	struct quattro		 *qfe_parent;	/* For Quattro cards                 */
461 	int			  qfe_ent;	/* Which instance on quattro         */
462 };
463 
464 /* Here are the happy flags. */
465 #define HFLAG_POLL                0x00000001      /* We are doing MIF polling          */
466 #define HFLAG_FENABLE             0x00000002      /* The MII frame is enabled          */
467 #define HFLAG_LANCE               0x00000004      /* We are using lance-mode           */
468 #define HFLAG_RXENABLE            0x00000008      /* Receiver is enabled               */
469 #define HFLAG_AUTO                0x00000010      /* Using auto-negotiation, 0 = force */
470 #define HFLAG_FULL                0x00000020      /* Full duplex enable                */
471 #define HFLAG_MACFULL             0x00000040      /* Using full duplex in the MAC      */
472 #define HFLAG_POLLENABLE          0x00000080      /* Actually try MIF polling          */
473 #define HFLAG_RXCV                0x00000100      /* XXX RXCV ENABLE                   */
474 #define HFLAG_INIT                0x00000200      /* Init called at least once         */
475 #define HFLAG_LINKUP              0x00000400      /* 1 = Link is up                    */
476 #define HFLAG_PCI                 0x00000800      /* PCI based Happy Meal              */
477 #define HFLAG_QUATTRO		  0x00001000      /* On QFE/Quattro card	       */
478 
479 #define HFLAG_20_21  (HFLAG_POLLENABLE | HFLAG_FENABLE)
480 #define HFLAG_NOT_A0 (HFLAG_POLLENABLE | HFLAG_FENABLE | HFLAG_LANCE | HFLAG_RXCV)
481 
482 /* Support for QFE/Quattro cards. */
483 struct quattro {
484 	struct net_device	*happy_meals[4];
485 
486 	/* This is either a sbus_dev or a pci_dev. */
487 	void			*quattro_dev;
488 
489 	struct quattro		*next;
490 
491 	/* PROM ranges, if any. */
492 #ifdef CONFIG_SBUS
493 	struct linux_prom_ranges  ranges[8];
494 #endif
495 	int			  nranges;
496 };
497 
498 /* We use this to acquire receive skb's that we can DMA directly into. */
499 #define ALIGNED_RX_SKB_ADDR(addr) \
500         ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
501 #define happy_meal_alloc_skb(__length, __gfp_flags) \
502 ({	struct sk_buff *__skb; \
503 	__skb = alloc_skb((__length) + 64, (__gfp_flags)); \
504 	if(__skb) { \
505 		int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \
506 		if(__offset) \
507 			skb_reserve(__skb, __offset); \
508 	} \
509 	__skb; \
510 })
511 
512 #endif /* !(_SUNHME_H) */
513