1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Socionext MN88443x series demodulator driver for ISDB-S/ISDB-T.
4 //
5 // Copyright (c) 2018 Socionext Inc.
6 
7 #include <linux/bitfield.h>
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/of_device.h>
12 #include <linux/regmap.h>
13 #include <media/dvb_math.h>
14 
15 #include "mn88443x.h"
16 
17 /* ISDB-S registers */
18 #define ATSIDU_S                                    0x2f
19 #define ATSIDL_S                                    0x30
20 #define TSSET_S                                     0x31
21 #define AGCREAD_S                                   0x5a
22 #define CPMON1_S                                    0x5e
23 #define   CPMON1_S_FSYNC                              BIT(5)
24 #define   CPMON1_S_ERRMON                             BIT(4)
25 #define   CPMON1_S_SIGOFF                             BIT(3)
26 #define   CPMON1_S_W2LOCK                             BIT(2)
27 #define   CPMON1_S_W1LOCK                             BIT(1)
28 #define   CPMON1_S_DW1LOCK                            BIT(0)
29 #define TRMON_S                                     0x60
30 #define BERCNFLG_S                                  0x68
31 #define   BERCNFLG_S_BERVRDY                          BIT(5)
32 #define   BERCNFLG_S_BERVCHK                          BIT(4)
33 #define   BERCNFLG_S_BERDRDY                          BIT(3)
34 #define   BERCNFLG_S_BERDCHK                          BIT(2)
35 #define CNRDXU_S                                    0x69
36 #define CNRDXL_S                                    0x6a
37 #define CNRDYU_S                                    0x6b
38 #define CNRDYL_S                                    0x6c
39 #define BERVRDU_S                                   0x71
40 #define BERVRDL_S                                   0x72
41 #define DOSET1_S                                    0x73
42 
43 /* Primary ISDB-T */
44 #define PLLASET1                                    0x00
45 #define PLLASET2                                    0x01
46 #define PLLBSET1                                    0x02
47 #define PLLBSET2                                    0x03
48 #define PLLSET                                      0x04
49 #define OUTCSET                                     0x08
50 #define   OUTCSET_CHDRV_8MA                           0xff
51 #define   OUTCSET_CHDRV_4MA                           0x00
52 #define PLDWSET                                     0x09
53 #define   PLDWSET_NORMAL                             0x00
54 #define   PLDWSET_PULLDOWN                           0xff
55 #define HIZSET1                                     0x0a
56 #define HIZSET2                                     0x0b
57 
58 /* Secondary ISDB-T (for MN884434 only) */
59 #define RCVSET                                      0x00
60 #define TSSET1_M                                    0x01
61 #define TSSET2_M                                    0x02
62 #define TSSET3_M                                    0x03
63 #define INTACSET                                    0x08
64 #define HIZSET3                                     0x0b
65 
66 /* ISDB-T registers */
67 #define TSSET1                                      0x05
68 #define   TSSET1_TSASEL_MASK                          GENMASK(4, 3)
69 #define   TSSET1_TSASEL_ISDBT                         (0x0 << 3)
70 #define   TSSET1_TSASEL_ISDBS                         (0x1 << 3)
71 #define   TSSET1_TSASEL_NONE                          (0x2 << 3)
72 #define   TSSET1_TSBSEL_MASK                          GENMASK(2, 1)
73 #define   TSSET1_TSBSEL_ISDBS                         (0x0 << 1)
74 #define   TSSET1_TSBSEL_ISDBT                         (0x1 << 1)
75 #define   TSSET1_TSBSEL_NONE                          (0x2 << 1)
76 #define TSSET2                                      0x06
77 #define TSSET3                                      0x07
78 #define   TSSET3_INTASEL_MASK                         GENMASK(7, 6)
79 #define   TSSET3_INTASEL_T                            (0x0 << 6)
80 #define   TSSET3_INTASEL_S                            (0x1 << 6)
81 #define   TSSET3_INTASEL_NONE                         (0x2 << 6)
82 #define   TSSET3_INTBSEL_MASK                         GENMASK(5, 4)
83 #define   TSSET3_INTBSEL_S                            (0x0 << 4)
84 #define   TSSET3_INTBSEL_T                            (0x1 << 4)
85 #define   TSSET3_INTBSEL_NONE                         (0x2 << 4)
86 #define OUTSET2                                     0x0d
87 #define PWDSET                                      0x0f
88 #define   PWDSET_OFDMPD_MASK                          GENMASK(3, 2)
89 #define   PWDSET_OFDMPD_DOWN                          BIT(3)
90 #define   PWDSET_PSKPD_MASK                           GENMASK(1, 0)
91 #define   PWDSET_PSKPD_DOWN                           BIT(1)
92 #define CLKSET1_T                                   0x11
93 #define MDSET_T                                     0x13
94 #define   MDSET_T_MDAUTO_MASK                         GENMASK(7, 4)
95 #define   MDSET_T_MDAUTO_AUTO                         (0xf << 4)
96 #define   MDSET_T_MDAUTO_MANUAL                       (0x0 << 4)
97 #define   MDSET_T_FFTS_MASK                           GENMASK(3, 2)
98 #define   MDSET_T_FFTS_MODE1                          (0x0 << 2)
99 #define   MDSET_T_FFTS_MODE2                          (0x1 << 2)
100 #define   MDSET_T_FFTS_MODE3                          (0x2 << 2)
101 #define   MDSET_T_GI_MASK                             GENMASK(1, 0)
102 #define   MDSET_T_GI_1_32                             (0x0 << 0)
103 #define   MDSET_T_GI_1_16                             (0x1 << 0)
104 #define   MDSET_T_GI_1_8                              (0x2 << 0)
105 #define   MDSET_T_GI_1_4                              (0x3 << 0)
106 #define MDASET_T                                    0x14
107 #define ADCSET1_T                                   0x20
108 #define   ADCSET1_T_REFSEL_MASK                       GENMASK(1, 0)
109 #define   ADCSET1_T_REFSEL_2V                         (0x3 << 0)
110 #define   ADCSET1_T_REFSEL_1_5V                       (0x2 << 0)
111 #define   ADCSET1_T_REFSEL_1V                         (0x1 << 0)
112 #define NCOFREQU_T                                  0x24
113 #define NCOFREQM_T                                  0x25
114 #define NCOFREQL_T                                  0x26
115 #define FADU_T                                      0x27
116 #define FADM_T                                      0x28
117 #define FADL_T                                      0x29
118 #define AGCSET2_T                                   0x2c
119 #define   AGCSET2_T_IFPOLINV_INC                      BIT(0)
120 #define   AGCSET2_T_RFPOLINV_INC                      BIT(1)
121 #define AGCV3_T                                     0x3e
122 #define MDRD_T                                      0xa2
123 #define   MDRD_T_SEGID_MASK                           GENMASK(5, 4)
124 #define   MDRD_T_SEGID_13                             (0x0 << 4)
125 #define   MDRD_T_SEGID_1                              (0x1 << 4)
126 #define   MDRD_T_SEGID_3                              (0x2 << 4)
127 #define   MDRD_T_FFTS_MASK                            GENMASK(3, 2)
128 #define   MDRD_T_FFTS_MODE1                           (0x0 << 2)
129 #define   MDRD_T_FFTS_MODE2                           (0x1 << 2)
130 #define   MDRD_T_FFTS_MODE3                           (0x2 << 2)
131 #define   MDRD_T_GI_MASK                              GENMASK(1, 0)
132 #define   MDRD_T_GI_1_32                              (0x0 << 0)
133 #define   MDRD_T_GI_1_16                              (0x1 << 0)
134 #define   MDRD_T_GI_1_8                               (0x2 << 0)
135 #define   MDRD_T_GI_1_4                               (0x3 << 0)
136 #define SSEQRD_T                                    0xa3
137 #define   SSEQRD_T_SSEQSTRD_MASK                      GENMASK(3, 0)
138 #define   SSEQRD_T_SSEQSTRD_RESET                     (0x0 << 0)
139 #define   SSEQRD_T_SSEQSTRD_TUNING                    (0x1 << 0)
140 #define   SSEQRD_T_SSEQSTRD_AGC                       (0x2 << 0)
141 #define   SSEQRD_T_SSEQSTRD_SEARCH                    (0x3 << 0)
142 #define   SSEQRD_T_SSEQSTRD_CLOCK_SYNC                (0x4 << 0)
143 #define   SSEQRD_T_SSEQSTRD_FREQ_SYNC                 (0x8 << 0)
144 #define   SSEQRD_T_SSEQSTRD_FRAME_SYNC                (0x9 << 0)
145 #define   SSEQRD_T_SSEQSTRD_SYNC                      (0xa << 0)
146 #define   SSEQRD_T_SSEQSTRD_LOCK                      (0xb << 0)
147 #define AGCRDU_T                                    0xa8
148 #define AGCRDL_T                                    0xa9
149 #define CNRDU_T                                     0xbe
150 #define CNRDL_T                                     0xbf
151 #define BERFLG_T                                    0xc0
152 #define   BERFLG_T_BERDRDY                            BIT(7)
153 #define   BERFLG_T_BERDCHK                            BIT(6)
154 #define   BERFLG_T_BERVRDYA                           BIT(5)
155 #define   BERFLG_T_BERVCHKA                           BIT(4)
156 #define   BERFLG_T_BERVRDYB                           BIT(3)
157 #define   BERFLG_T_BERVCHKB                           BIT(2)
158 #define   BERFLG_T_BERVRDYC                           BIT(1)
159 #define   BERFLG_T_BERVCHKC                           BIT(0)
160 #define BERRDU_T                                    0xc1
161 #define BERRDM_T                                    0xc2
162 #define BERRDL_T                                    0xc3
163 #define BERLENRDU_T                                 0xc4
164 #define BERLENRDL_T                                 0xc5
165 #define ERRFLG_T                                    0xc6
166 #define   ERRFLG_T_BERDOVF                            BIT(7)
167 #define   ERRFLG_T_BERVOVFA                           BIT(6)
168 #define   ERRFLG_T_BERVOVFB                           BIT(5)
169 #define   ERRFLG_T_BERVOVFC                           BIT(4)
170 #define   ERRFLG_T_NERRFA                             BIT(3)
171 #define   ERRFLG_T_NERRFB                             BIT(2)
172 #define   ERRFLG_T_NERRFC                             BIT(1)
173 #define   ERRFLG_T_NERRF                              BIT(0)
174 #define DOSET1_T                                    0xcf
175 
176 #define CLK_LOW            4000000
177 #define CLK_DIRECT         20200000
178 #define CLK_MAX            25410000
179 
180 #define S_T_FREQ           8126984 /* 512 / 63 MHz */
181 
182 struct mn88443x_spec {
183 	bool primary;
184 };
185 
186 struct mn88443x_priv {
187 	const struct mn88443x_spec *spec;
188 
189 	struct dvb_frontend fe;
190 	struct clk *mclk;
191 	struct gpio_desc *reset_gpio;
192 	u32 clk_freq;
193 	u32 if_freq;
194 
195 	/* Common */
196 	bool use_clkbuf;
197 
198 	/* ISDB-S */
199 	struct i2c_client *client_s;
200 	struct regmap *regmap_s;
201 
202 	/* ISDB-T */
203 	struct i2c_client *client_t;
204 	struct regmap *regmap_t;
205 };
206 
mn88443x_cmn_power_on(struct mn88443x_priv * chip)207 static int mn88443x_cmn_power_on(struct mn88443x_priv *chip)
208 {
209 	struct device *dev = &chip->client_s->dev;
210 	struct regmap *r_t = chip->regmap_t;
211 	int ret;
212 
213 	ret = clk_prepare_enable(chip->mclk);
214 	if (ret) {
215 		dev_err(dev, "Failed to prepare and enable mclk: %d\n",
216 			ret);
217 		return ret;
218 	}
219 
220 	gpiod_set_value_cansleep(chip->reset_gpio, 1);
221 	usleep_range(100, 1000);
222 	gpiod_set_value_cansleep(chip->reset_gpio, 0);
223 
224 	if (chip->spec->primary) {
225 		regmap_write(r_t, OUTCSET, OUTCSET_CHDRV_8MA);
226 		regmap_write(r_t, PLDWSET, PLDWSET_NORMAL);
227 		regmap_write(r_t, HIZSET1, 0x80);
228 		regmap_write(r_t, HIZSET2, 0xe0);
229 	} else {
230 		regmap_write(r_t, HIZSET3, 0x8f);
231 	}
232 
233 	return 0;
234 }
235 
mn88443x_cmn_power_off(struct mn88443x_priv * chip)236 static void mn88443x_cmn_power_off(struct mn88443x_priv *chip)
237 {
238 	gpiod_set_value_cansleep(chip->reset_gpio, 1);
239 
240 	clk_disable_unprepare(chip->mclk);
241 }
242 
mn88443x_s_sleep(struct mn88443x_priv * chip)243 static void mn88443x_s_sleep(struct mn88443x_priv *chip)
244 {
245 	struct regmap *r_t = chip->regmap_t;
246 
247 	regmap_update_bits(r_t, PWDSET, PWDSET_PSKPD_MASK,
248 			   PWDSET_PSKPD_DOWN);
249 }
250 
mn88443x_s_wake(struct mn88443x_priv * chip)251 static void mn88443x_s_wake(struct mn88443x_priv *chip)
252 {
253 	struct regmap *r_t = chip->regmap_t;
254 
255 	regmap_update_bits(r_t, PWDSET, PWDSET_PSKPD_MASK, 0);
256 }
257 
mn88443x_s_tune(struct mn88443x_priv * chip,struct dtv_frontend_properties * c)258 static void mn88443x_s_tune(struct mn88443x_priv *chip,
259 			    struct dtv_frontend_properties *c)
260 {
261 	struct regmap *r_s = chip->regmap_s;
262 
263 	regmap_write(r_s, ATSIDU_S, c->stream_id >> 8);
264 	regmap_write(r_s, ATSIDL_S, c->stream_id);
265 	regmap_write(r_s, TSSET_S, 0);
266 }
267 
mn88443x_s_read_status(struct mn88443x_priv * chip,struct dtv_frontend_properties * c,enum fe_status * status)268 static int mn88443x_s_read_status(struct mn88443x_priv *chip,
269 				  struct dtv_frontend_properties *c,
270 				  enum fe_status *status)
271 {
272 	struct regmap *r_s = chip->regmap_s;
273 	u32 cpmon, tmpu, tmpl, flg;
274 	u64 tmp;
275 
276 	/* Sync detection */
277 	regmap_read(r_s, CPMON1_S, &cpmon);
278 
279 	*status = 0;
280 	if (cpmon & CPMON1_S_FSYNC)
281 		*status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
282 	if (cpmon & CPMON1_S_W2LOCK)
283 		*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
284 
285 	/* Signal strength */
286 	c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
287 
288 	if (*status & FE_HAS_SIGNAL) {
289 		u32 agc;
290 
291 		regmap_read(r_s, AGCREAD_S, &tmpu);
292 		agc = tmpu << 8;
293 
294 		c->strength.len = 1;
295 		c->strength.stat[0].scale = FE_SCALE_RELATIVE;
296 		c->strength.stat[0].uvalue = agc;
297 	}
298 
299 	/* C/N rate */
300 	c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
301 
302 	if (*status & FE_HAS_VITERBI) {
303 		u32 cnr = 0, x, y, d;
304 		u64 d_3 = 0;
305 
306 		regmap_read(r_s, CNRDXU_S, &tmpu);
307 		regmap_read(r_s, CNRDXL_S, &tmpl);
308 		x = (tmpu << 8) | tmpl;
309 		regmap_read(r_s, CNRDYU_S, &tmpu);
310 		regmap_read(r_s, CNRDYL_S, &tmpl);
311 		y = (tmpu << 8) | tmpl;
312 
313 		/* CNR[dB]: 10 * log10(D) - 30.74 / D^3 - 3 */
314 		/*   D = x^2 / (2^15 * y - x^2) */
315 		d = (y << 15) - x * x;
316 		if (d > 0) {
317 			/* (2^4 * D)^3 = 2^12 * D^3 */
318 			/* 3.074 * 2^(12 + 24) = 211243671486 */
319 			d_3 = div_u64(16 * x * x, d);
320 			d_3 = d_3 * d_3 * d_3;
321 			if (d_3)
322 				d_3 = div_u64(211243671486ULL, d_3);
323 		}
324 
325 		if (d_3) {
326 			/* 0.3 * 2^24 = 5033164 */
327 			tmp = (s64)2 * intlog10(x) - intlog10(abs(d)) - d_3
328 				- 5033164;
329 			cnr = div_u64(tmp * 10000, 1 << 24);
330 		}
331 
332 		if (cnr) {
333 			c->cnr.len = 1;
334 			c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
335 			c->cnr.stat[0].uvalue = cnr;
336 		}
337 	}
338 
339 	/* BER */
340 	c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
341 	c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
342 
343 	regmap_read(r_s, BERCNFLG_S, &flg);
344 
345 	if ((*status & FE_HAS_VITERBI) && (flg & BERCNFLG_S_BERVRDY)) {
346 		u32 bit_err, bit_cnt;
347 
348 		regmap_read(r_s, BERVRDU_S, &tmpu);
349 		regmap_read(r_s, BERVRDL_S, &tmpl);
350 		bit_err = (tmpu << 8) | tmpl;
351 		bit_cnt = (1 << 13) * 204;
352 
353 		if (bit_cnt) {
354 			c->post_bit_error.len = 1;
355 			c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
356 			c->post_bit_error.stat[0].uvalue = bit_err;
357 			c->post_bit_count.len = 1;
358 			c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
359 			c->post_bit_count.stat[0].uvalue = bit_cnt;
360 		}
361 	}
362 
363 	return 0;
364 }
365 
mn88443x_t_sleep(struct mn88443x_priv * chip)366 static void mn88443x_t_sleep(struct mn88443x_priv *chip)
367 {
368 	struct regmap *r_t = chip->regmap_t;
369 
370 	regmap_update_bits(r_t, PWDSET, PWDSET_OFDMPD_MASK,
371 			   PWDSET_OFDMPD_DOWN);
372 }
373 
mn88443x_t_wake(struct mn88443x_priv * chip)374 static void mn88443x_t_wake(struct mn88443x_priv *chip)
375 {
376 	struct regmap *r_t = chip->regmap_t;
377 
378 	regmap_update_bits(r_t, PWDSET, PWDSET_OFDMPD_MASK, 0);
379 }
380 
mn88443x_t_is_valid_clk(u32 adckt,u32 if_freq)381 static bool mn88443x_t_is_valid_clk(u32 adckt, u32 if_freq)
382 {
383 	if (if_freq == DIRECT_IF_57MHZ) {
384 		if (adckt >= CLK_DIRECT && adckt <= 21000000)
385 			return true;
386 		if (adckt >= 25300000 && adckt <= CLK_MAX)
387 			return true;
388 	} else if (if_freq == DIRECT_IF_44MHZ) {
389 		if (adckt >= 25000000 && adckt <= CLK_MAX)
390 			return true;
391 	} else if (if_freq >= LOW_IF_4MHZ && if_freq < DIRECT_IF_44MHZ) {
392 		if (adckt >= CLK_DIRECT && adckt <= CLK_MAX)
393 			return true;
394 	}
395 
396 	return false;
397 }
398 
mn88443x_t_set_freq(struct mn88443x_priv * chip)399 static int mn88443x_t_set_freq(struct mn88443x_priv *chip)
400 {
401 	struct device *dev = &chip->client_s->dev;
402 	struct regmap *r_t = chip->regmap_t;
403 	s64 adckt, nco, ad_t;
404 	u32 m, v;
405 
406 	/* Clock buffer (but not supported) or XTAL */
407 	if (chip->clk_freq >= CLK_LOW && chip->clk_freq < CLK_DIRECT) {
408 		chip->use_clkbuf = true;
409 		regmap_write(r_t, CLKSET1_T, 0x07);
410 
411 		adckt = 0;
412 	} else {
413 		chip->use_clkbuf = false;
414 		regmap_write(r_t, CLKSET1_T, 0x00);
415 
416 		adckt = chip->clk_freq;
417 	}
418 	if (!mn88443x_t_is_valid_clk(adckt, chip->if_freq)) {
419 		dev_err(dev, "Invalid clock, CLK:%d, ADCKT:%lld, IF:%d\n",
420 			chip->clk_freq, adckt, chip->if_freq);
421 		return -EINVAL;
422 	}
423 
424 	/* Direct IF or Low IF */
425 	if (chip->if_freq == DIRECT_IF_57MHZ ||
426 	    chip->if_freq == DIRECT_IF_44MHZ)
427 		nco = adckt * 2 - chip->if_freq;
428 	else
429 		nco = -((s64)chip->if_freq);
430 	nco = div_s64(nco << 24, adckt);
431 	ad_t = div_s64(adckt << 22, S_T_FREQ);
432 
433 	regmap_write(r_t, NCOFREQU_T, nco >> 16);
434 	regmap_write(r_t, NCOFREQM_T, nco >> 8);
435 	regmap_write(r_t, NCOFREQL_T, nco);
436 	regmap_write(r_t, FADU_T, ad_t >> 16);
437 	regmap_write(r_t, FADM_T, ad_t >> 8);
438 	regmap_write(r_t, FADL_T, ad_t);
439 
440 	/* Level of IF */
441 	m = ADCSET1_T_REFSEL_MASK;
442 	v = ADCSET1_T_REFSEL_1_5V;
443 	regmap_update_bits(r_t, ADCSET1_T, m, v);
444 
445 	/* Polarity of AGC */
446 	v = AGCSET2_T_IFPOLINV_INC | AGCSET2_T_RFPOLINV_INC;
447 	regmap_update_bits(r_t, AGCSET2_T, v, v);
448 
449 	/* Lower output level of AGC */
450 	regmap_write(r_t, AGCV3_T, 0x00);
451 
452 	regmap_write(r_t, MDSET_T, 0xfa);
453 
454 	return 0;
455 }
456 
mn88443x_t_tune(struct mn88443x_priv * chip,struct dtv_frontend_properties * c)457 static void mn88443x_t_tune(struct mn88443x_priv *chip,
458 			    struct dtv_frontend_properties *c)
459 {
460 	struct regmap *r_t = chip->regmap_t;
461 	u32 m, v;
462 
463 	m = MDSET_T_MDAUTO_MASK | MDSET_T_FFTS_MASK | MDSET_T_GI_MASK;
464 	v = MDSET_T_MDAUTO_AUTO | MDSET_T_FFTS_MODE3 | MDSET_T_GI_1_8;
465 	regmap_update_bits(r_t, MDSET_T, m, v);
466 
467 	regmap_write(r_t, MDASET_T, 0);
468 }
469 
mn88443x_t_read_status(struct mn88443x_priv * chip,struct dtv_frontend_properties * c,enum fe_status * status)470 static int mn88443x_t_read_status(struct mn88443x_priv *chip,
471 				  struct dtv_frontend_properties *c,
472 				  enum fe_status *status)
473 {
474 	struct regmap *r_t = chip->regmap_t;
475 	u32 seqrd, st, flg, tmpu, tmpm, tmpl;
476 	u64 tmp;
477 
478 	/* Sync detection */
479 	regmap_read(r_t, SSEQRD_T, &seqrd);
480 	st = seqrd & SSEQRD_T_SSEQSTRD_MASK;
481 
482 	*status = 0;
483 	if (st >= SSEQRD_T_SSEQSTRD_SYNC)
484 		*status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
485 	if (st >= SSEQRD_T_SSEQSTRD_FRAME_SYNC)
486 		*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
487 
488 	/* Signal strength */
489 	c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
490 
491 	if (*status & FE_HAS_SIGNAL) {
492 		u32 agc;
493 
494 		regmap_read(r_t, AGCRDU_T, &tmpu);
495 		regmap_read(r_t, AGCRDL_T, &tmpl);
496 		agc = (tmpu << 8) | tmpl;
497 
498 		c->strength.len = 1;
499 		c->strength.stat[0].scale = FE_SCALE_RELATIVE;
500 		c->strength.stat[0].uvalue = agc;
501 	}
502 
503 	/* C/N rate */
504 	c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
505 
506 	if (*status & FE_HAS_VITERBI) {
507 		u32 cnr;
508 
509 		regmap_read(r_t, CNRDU_T, &tmpu);
510 		regmap_read(r_t, CNRDL_T, &tmpl);
511 
512 		if (tmpu || tmpl) {
513 			/* CNR[dB]: 10 * (log10(65536 / value) + 0.2) */
514 			/* intlog10(65536) = 80807124, 0.2 * 2^24 = 3355443 */
515 			tmp = (u64)80807124 - intlog10((tmpu << 8) | tmpl)
516 				+ 3355443;
517 			cnr = div_u64(tmp * 10000, 1 << 24);
518 		} else {
519 			cnr = 0;
520 		}
521 
522 		c->cnr.len = 1;
523 		c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
524 		c->cnr.stat[0].uvalue = cnr;
525 	}
526 
527 	/* BER */
528 	c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
529 	c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
530 
531 	regmap_read(r_t, BERFLG_T, &flg);
532 
533 	if ((*status & FE_HAS_VITERBI) && (flg & BERFLG_T_BERVRDYA)) {
534 		u32 bit_err, bit_cnt;
535 
536 		regmap_read(r_t, BERRDU_T, &tmpu);
537 		regmap_read(r_t, BERRDM_T, &tmpm);
538 		regmap_read(r_t, BERRDL_T, &tmpl);
539 		bit_err = (tmpu << 16) | (tmpm << 8) | tmpl;
540 
541 		regmap_read(r_t, BERLENRDU_T, &tmpu);
542 		regmap_read(r_t, BERLENRDL_T, &tmpl);
543 		bit_cnt = ((tmpu << 8) | tmpl) * 203 * 8;
544 
545 		if (bit_cnt) {
546 			c->post_bit_error.len = 1;
547 			c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
548 			c->post_bit_error.stat[0].uvalue = bit_err;
549 			c->post_bit_count.len = 1;
550 			c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
551 			c->post_bit_count.stat[0].uvalue = bit_cnt;
552 		}
553 	}
554 
555 	return 0;
556 }
557 
mn88443x_sleep(struct dvb_frontend * fe)558 static int mn88443x_sleep(struct dvb_frontend *fe)
559 {
560 	struct mn88443x_priv *chip = fe->demodulator_priv;
561 
562 	mn88443x_s_sleep(chip);
563 	mn88443x_t_sleep(chip);
564 
565 	return 0;
566 }
567 
mn88443x_set_frontend(struct dvb_frontend * fe)568 static int mn88443x_set_frontend(struct dvb_frontend *fe)
569 {
570 	struct mn88443x_priv *chip = fe->demodulator_priv;
571 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
572 	struct regmap *r_s = chip->regmap_s;
573 	struct regmap *r_t = chip->regmap_t;
574 	u8 tssel = 0, intsel = 0;
575 
576 	if (c->delivery_system == SYS_ISDBS) {
577 		mn88443x_s_wake(chip);
578 		mn88443x_t_sleep(chip);
579 
580 		tssel = TSSET1_TSASEL_ISDBS;
581 		intsel = TSSET3_INTASEL_S;
582 	} else if (c->delivery_system == SYS_ISDBT) {
583 		mn88443x_s_sleep(chip);
584 		mn88443x_t_wake(chip);
585 
586 		mn88443x_t_set_freq(chip);
587 
588 		tssel = TSSET1_TSASEL_ISDBT;
589 		intsel = TSSET3_INTASEL_T;
590 	}
591 
592 	regmap_update_bits(r_t, TSSET1,
593 			   TSSET1_TSASEL_MASK | TSSET1_TSBSEL_MASK,
594 			   tssel | TSSET1_TSBSEL_NONE);
595 	regmap_write(r_t, TSSET2, 0);
596 	regmap_update_bits(r_t, TSSET3,
597 			   TSSET3_INTASEL_MASK | TSSET3_INTBSEL_MASK,
598 			   intsel | TSSET3_INTBSEL_NONE);
599 
600 	regmap_write(r_t, DOSET1_T, 0x95);
601 	regmap_write(r_s, DOSET1_S, 0x80);
602 
603 	if (c->delivery_system == SYS_ISDBS)
604 		mn88443x_s_tune(chip, c);
605 	else if (c->delivery_system == SYS_ISDBT)
606 		mn88443x_t_tune(chip, c);
607 
608 	if (fe->ops.tuner_ops.set_params) {
609 		if (fe->ops.i2c_gate_ctrl)
610 			fe->ops.i2c_gate_ctrl(fe, 1);
611 		fe->ops.tuner_ops.set_params(fe);
612 		if (fe->ops.i2c_gate_ctrl)
613 			fe->ops.i2c_gate_ctrl(fe, 0);
614 	}
615 
616 	return 0;
617 }
618 
mn88443x_get_tune_settings(struct dvb_frontend * fe,struct dvb_frontend_tune_settings * s)619 static int mn88443x_get_tune_settings(struct dvb_frontend *fe,
620 				      struct dvb_frontend_tune_settings *s)
621 {
622 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
623 
624 	s->min_delay_ms = 850;
625 
626 	if (c->delivery_system == SYS_ISDBS) {
627 		s->max_drift = 30000 * 2 + 1;
628 		s->step_size = 30000;
629 	} else if (c->delivery_system == SYS_ISDBT) {
630 		s->max_drift = 142857 * 2 + 1;
631 		s->step_size = 142857 * 2;
632 	}
633 
634 	return 0;
635 }
636 
mn88443x_read_status(struct dvb_frontend * fe,enum fe_status * status)637 static int mn88443x_read_status(struct dvb_frontend *fe, enum fe_status *status)
638 {
639 	struct mn88443x_priv *chip = fe->demodulator_priv;
640 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
641 
642 	if (c->delivery_system == SYS_ISDBS)
643 		return mn88443x_s_read_status(chip, c, status);
644 
645 	if (c->delivery_system == SYS_ISDBT)
646 		return mn88443x_t_read_status(chip, c, status);
647 
648 	return -EINVAL;
649 }
650 
651 static const struct dvb_frontend_ops mn88443x_ops = {
652 	.delsys = { SYS_ISDBS, SYS_ISDBT },
653 	.info = {
654 		.name = "Socionext MN88443x",
655 		.frequency_min_hz =  470 * MHz,
656 		.frequency_max_hz = 2071 * MHz,
657 		.symbol_rate_min  = 28860000,
658 		.symbol_rate_max  = 28860000,
659 		.caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO |
660 			FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
661 			FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
662 	},
663 
664 	.sleep                   = mn88443x_sleep,
665 	.set_frontend            = mn88443x_set_frontend,
666 	.get_tune_settings       = mn88443x_get_tune_settings,
667 	.read_status             = mn88443x_read_status,
668 };
669 
670 static const struct regmap_config regmap_config = {
671 	.reg_bits   = 8,
672 	.val_bits   = 8,
673 	.cache_type = REGCACHE_NONE,
674 };
675 
mn88443x_probe(struct i2c_client * client,const struct i2c_device_id * id)676 static int mn88443x_probe(struct i2c_client *client,
677 			  const struct i2c_device_id *id)
678 {
679 	struct mn88443x_config *conf = client->dev.platform_data;
680 	struct mn88443x_priv *chip;
681 	struct device *dev = &client->dev;
682 	int ret;
683 
684 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
685 	if (!chip)
686 		return -ENOMEM;
687 
688 	if (dev->of_node)
689 		chip->spec = of_device_get_match_data(dev);
690 	else
691 		chip->spec = (struct mn88443x_spec *)id->driver_data;
692 	if (!chip->spec)
693 		return -EINVAL;
694 
695 	chip->mclk = devm_clk_get(dev, "mclk");
696 	if (IS_ERR(chip->mclk) && !conf) {
697 		dev_err(dev, "Failed to request mclk: %ld\n",
698 			PTR_ERR(chip->mclk));
699 		return PTR_ERR(chip->mclk);
700 	}
701 
702 	ret = of_property_read_u32(dev->of_node, "if-frequency",
703 				   &chip->if_freq);
704 	if (ret && !conf) {
705 		dev_err(dev, "Failed to load IF frequency: %d.\n", ret);
706 		return ret;
707 	}
708 
709 	chip->reset_gpio = devm_gpiod_get_optional(dev, "reset",
710 						   GPIOD_OUT_HIGH);
711 	if (IS_ERR(chip->reset_gpio)) {
712 		dev_err(dev, "Failed to request reset_gpio: %ld\n",
713 			PTR_ERR(chip->reset_gpio));
714 		return PTR_ERR(chip->reset_gpio);
715 	}
716 
717 	if (conf) {
718 		chip->mclk = conf->mclk;
719 		chip->if_freq = conf->if_freq;
720 		chip->reset_gpio = conf->reset_gpio;
721 
722 		*conf->fe = &chip->fe;
723 	}
724 
725 	chip->client_s = client;
726 	chip->regmap_s = devm_regmap_init_i2c(chip->client_s, &regmap_config);
727 	if (IS_ERR(chip->regmap_s))
728 		return PTR_ERR(chip->regmap_s);
729 
730 	/*
731 	 * Chip has two I2C addresses for each satellite/terrestrial system.
732 	 * ISDB-T uses address ISDB-S + 4, so we register a dummy client.
733 	 */
734 	chip->client_t = i2c_new_dummy_device(client->adapter, client->addr + 4);
735 	if (IS_ERR(chip->client_t))
736 		return PTR_ERR(chip->client_t);
737 
738 	chip->regmap_t = devm_regmap_init_i2c(chip->client_t, &regmap_config);
739 	if (IS_ERR(chip->regmap_t)) {
740 		ret = PTR_ERR(chip->regmap_t);
741 		goto err_i2c_t;
742 	}
743 
744 	chip->clk_freq = clk_get_rate(chip->mclk);
745 
746 	memcpy(&chip->fe.ops, &mn88443x_ops, sizeof(mn88443x_ops));
747 	chip->fe.demodulator_priv = chip;
748 	i2c_set_clientdata(client, chip);
749 
750 	ret = mn88443x_cmn_power_on(chip);
751 	if (ret)
752 		goto err_i2c_t;
753 
754 	mn88443x_s_sleep(chip);
755 	mn88443x_t_sleep(chip);
756 
757 	return 0;
758 
759 err_i2c_t:
760 	i2c_unregister_device(chip->client_t);
761 
762 	return ret;
763 }
764 
mn88443x_remove(struct i2c_client * client)765 static void mn88443x_remove(struct i2c_client *client)
766 {
767 	struct mn88443x_priv *chip = i2c_get_clientdata(client);
768 
769 	mn88443x_cmn_power_off(chip);
770 
771 	i2c_unregister_device(chip->client_t);
772 }
773 
774 static const struct mn88443x_spec mn88443x_spec_pri = {
775 	.primary = true,
776 };
777 
778 static const struct mn88443x_spec mn88443x_spec_sec = {
779 	.primary = false,
780 };
781 
782 static const struct of_device_id mn88443x_of_match[] = {
783 	{ .compatible = "socionext,mn884433",   .data = &mn88443x_spec_pri, },
784 	{ .compatible = "socionext,mn884434-0", .data = &mn88443x_spec_pri, },
785 	{ .compatible = "socionext,mn884434-1", .data = &mn88443x_spec_sec, },
786 	{}
787 };
788 MODULE_DEVICE_TABLE(of, mn88443x_of_match);
789 
790 static const struct i2c_device_id mn88443x_i2c_id[] = {
791 	{ "mn884433",   (kernel_ulong_t)&mn88443x_spec_pri },
792 	{ "mn884434-0", (kernel_ulong_t)&mn88443x_spec_pri },
793 	{ "mn884434-1", (kernel_ulong_t)&mn88443x_spec_sec },
794 	{}
795 };
796 MODULE_DEVICE_TABLE(i2c, mn88443x_i2c_id);
797 
798 static struct i2c_driver mn88443x_driver = {
799 	.driver = {
800 		.name = "mn88443x",
801 		.of_match_table = of_match_ptr(mn88443x_of_match),
802 	},
803 	.probe    = mn88443x_probe,
804 	.remove   = mn88443x_remove,
805 	.id_table = mn88443x_i2c_id,
806 };
807 
808 module_i2c_driver(mn88443x_driver);
809 
810 MODULE_AUTHOR("Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>");
811 MODULE_DESCRIPTION("Socionext MN88443x series demodulator driver.");
812 MODULE_LICENSE("GPL v2");
813