1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 3 /* Authors: Cheng Xu <chengyou@linux.alibaba.com> */ 4 /* Kai Shen <kaishen@linux.alibaba.com> */ 5 /* Copyright (c) 2020-2022, Alibaba Group. */ 6 7 #ifndef __ERDMA_HW_H__ 8 #define __ERDMA_HW_H__ 9 10 #include <linux/kernel.h> 11 #include <linux/types.h> 12 13 /* PCIe device related definition. */ 14 #define PCI_VENDOR_ID_ALIBABA 0x1ded 15 16 #define ERDMA_PCI_WIDTH 64 17 #define ERDMA_FUNC_BAR 0 18 #define ERDMA_MISX_BAR 2 19 20 #define ERDMA_BAR_MASK (BIT(ERDMA_FUNC_BAR) | BIT(ERDMA_MISX_BAR)) 21 22 /* MSI-X related. */ 23 #define ERDMA_NUM_MSIX_VEC 32U 24 #define ERDMA_MSIX_VECTOR_CMDQ 0 25 26 /* PCIe Bar0 Registers. */ 27 #define ERDMA_REGS_VERSION_REG 0x0 28 #define ERDMA_REGS_DEV_CTRL_REG 0x10 29 #define ERDMA_REGS_DEV_ST_REG 0x14 30 #define ERDMA_REGS_NETDEV_MAC_L_REG 0x18 31 #define ERDMA_REGS_NETDEV_MAC_H_REG 0x1C 32 #define ERDMA_REGS_CMDQ_SQ_ADDR_L_REG 0x20 33 #define ERDMA_REGS_CMDQ_SQ_ADDR_H_REG 0x24 34 #define ERDMA_REGS_CMDQ_CQ_ADDR_L_REG 0x28 35 #define ERDMA_REGS_CMDQ_CQ_ADDR_H_REG 0x2C 36 #define ERDMA_REGS_CMDQ_DEPTH_REG 0x30 37 #define ERDMA_REGS_CMDQ_EQ_DEPTH_REG 0x34 38 #define ERDMA_REGS_CMDQ_EQ_ADDR_L_REG 0x38 39 #define ERDMA_REGS_CMDQ_EQ_ADDR_H_REG 0x3C 40 #define ERDMA_REGS_AEQ_ADDR_L_REG 0x40 41 #define ERDMA_REGS_AEQ_ADDR_H_REG 0x44 42 #define ERDMA_REGS_AEQ_DEPTH_REG 0x48 43 #define ERDMA_REGS_GRP_NUM_REG 0x4c 44 #define ERDMA_REGS_AEQ_DB_REG 0x50 45 #define ERDMA_CMDQ_SQ_DB_HOST_ADDR_REG 0x60 46 #define ERDMA_CMDQ_CQ_DB_HOST_ADDR_REG 0x68 47 #define ERDMA_CMDQ_EQ_DB_HOST_ADDR_REG 0x70 48 #define ERDMA_AEQ_DB_HOST_ADDR_REG 0x78 49 #define ERDMA_REGS_STATS_TSO_IN_PKTS_REG 0x80 50 #define ERDMA_REGS_STATS_TSO_OUT_PKTS_REG 0x88 51 #define ERDMA_REGS_STATS_TSO_OUT_BYTES_REG 0x90 52 #define ERDMA_REGS_STATS_TX_DROP_PKTS_REG 0x98 53 #define ERDMA_REGS_STATS_TX_BPS_METER_DROP_PKTS_REG 0xa0 54 #define ERDMA_REGS_STATS_TX_PPS_METER_DROP_PKTS_REG 0xa8 55 #define ERDMA_REGS_STATS_RX_PKTS_REG 0xc0 56 #define ERDMA_REGS_STATS_RX_BYTES_REG 0xc8 57 #define ERDMA_REGS_STATS_RX_DROP_PKTS_REG 0xd0 58 #define ERDMA_REGS_STATS_RX_BPS_METER_DROP_PKTS_REG 0xd8 59 #define ERDMA_REGS_STATS_RX_PPS_METER_DROP_PKTS_REG 0xe0 60 #define ERDMA_REGS_CEQ_DB_BASE_REG 0x100 61 #define ERDMA_CMDQ_SQDB_REG 0x200 62 #define ERDMA_CMDQ_CQDB_REG 0x300 63 64 /* DEV_CTRL_REG details. */ 65 #define ERDMA_REG_DEV_CTRL_RESET_MASK 0x00000001 66 #define ERDMA_REG_DEV_CTRL_INIT_MASK 0x00000002 67 68 /* DEV_ST_REG details. */ 69 #define ERDMA_REG_DEV_ST_RESET_DONE_MASK 0x00000001U 70 #define ERDMA_REG_DEV_ST_INIT_DONE_MASK 0x00000002U 71 72 /* eRDMA PCIe DBs definition. */ 73 #define ERDMA_BAR_DB_SPACE_BASE 4096 74 75 #define ERDMA_BAR_SQDB_SPACE_OFFSET ERDMA_BAR_DB_SPACE_BASE 76 #define ERDMA_BAR_SQDB_SPACE_SIZE (384 * 1024) 77 78 #define ERDMA_BAR_RQDB_SPACE_OFFSET \ 79 (ERDMA_BAR_SQDB_SPACE_OFFSET + ERDMA_BAR_SQDB_SPACE_SIZE) 80 #define ERDMA_BAR_RQDB_SPACE_SIZE (96 * 1024) 81 82 #define ERDMA_BAR_CQDB_SPACE_OFFSET \ 83 (ERDMA_BAR_RQDB_SPACE_OFFSET + ERDMA_BAR_RQDB_SPACE_SIZE) 84 85 /* Doorbell page resources related. */ 86 /* 87 * Max # of parallelly issued directSQE is 3072 per device, 88 * hardware organizes this into 24 group, per group has 128 credits. 89 */ 90 #define ERDMA_DWQE_MAX_GRP_CNT 24 91 #define ERDMA_DWQE_NUM_PER_GRP 128 92 93 #define ERDMA_DWQE_TYPE0_CNT 64 94 #define ERDMA_DWQE_TYPE1_CNT 496 95 /* type1 DB contains 2 DBs, takes 256Byte. */ 96 #define ERDMA_DWQE_TYPE1_CNT_PER_PAGE 16 97 98 #define ERDMA_SDB_SHARED_PAGE_INDEX 95 99 100 /* Doorbell related. */ 101 #define ERDMA_DB_SIZE 8 102 103 #define ERDMA_CQDB_IDX_MASK GENMASK_ULL(63, 56) 104 #define ERDMA_CQDB_CQN_MASK GENMASK_ULL(55, 32) 105 #define ERDMA_CQDB_ARM_MASK BIT_ULL(31) 106 #define ERDMA_CQDB_SOL_MASK BIT_ULL(30) 107 #define ERDMA_CQDB_CMDSN_MASK GENMASK_ULL(29, 28) 108 #define ERDMA_CQDB_CI_MASK GENMASK_ULL(23, 0) 109 110 #define ERDMA_EQDB_ARM_MASK BIT(31) 111 #define ERDMA_EQDB_CI_MASK GENMASK_ULL(23, 0) 112 113 #define ERDMA_PAGE_SIZE_SUPPORT 0x7FFFF000 114 115 /* WQE related. */ 116 #define EQE_SIZE 16 117 #define EQE_SHIFT 4 118 #define RQE_SIZE 32 119 #define RQE_SHIFT 5 120 #define CQE_SIZE 32 121 #define CQE_SHIFT 5 122 #define SQEBB_SIZE 32 123 #define SQEBB_SHIFT 5 124 #define SQEBB_MASK (~(SQEBB_SIZE - 1)) 125 #define SQEBB_ALIGN(size) ((size + SQEBB_SIZE - 1) & SQEBB_MASK) 126 #define SQEBB_COUNT(size) (SQEBB_ALIGN(size) >> SQEBB_SHIFT) 127 128 #define ERDMA_MAX_SQE_SIZE 128 129 #define ERDMA_MAX_WQEBB_PER_SQE 4 130 131 /* CMDQ related. */ 132 #define ERDMA_CMDQ_MAX_OUTSTANDING 128 133 #define ERDMA_CMDQ_SQE_SIZE 64 134 135 /* cmdq sub module definition. */ 136 enum CMDQ_WQE_SUB_MOD { 137 CMDQ_SUBMOD_RDMA = 0, 138 CMDQ_SUBMOD_COMMON = 1 139 }; 140 141 enum CMDQ_RDMA_OPCODE { 142 CMDQ_OPCODE_QUERY_DEVICE = 0, 143 CMDQ_OPCODE_CREATE_QP = 1, 144 CMDQ_OPCODE_DESTROY_QP = 2, 145 CMDQ_OPCODE_MODIFY_QP = 3, 146 CMDQ_OPCODE_CREATE_CQ = 4, 147 CMDQ_OPCODE_DESTROY_CQ = 5, 148 CMDQ_OPCODE_REG_MR = 8, 149 CMDQ_OPCODE_DEREG_MR = 9 150 }; 151 152 enum CMDQ_COMMON_OPCODE { 153 CMDQ_OPCODE_CREATE_EQ = 0, 154 CMDQ_OPCODE_DESTROY_EQ = 1, 155 CMDQ_OPCODE_QUERY_FW_INFO = 2, 156 CMDQ_OPCODE_CONF_MTU = 3, 157 }; 158 159 /* cmdq-SQE HDR */ 160 #define ERDMA_CMD_HDR_WQEBB_CNT_MASK GENMASK_ULL(54, 52) 161 #define ERDMA_CMD_HDR_CONTEXT_COOKIE_MASK GENMASK_ULL(47, 32) 162 #define ERDMA_CMD_HDR_SUB_MOD_MASK GENMASK_ULL(25, 24) 163 #define ERDMA_CMD_HDR_OPCODE_MASK GENMASK_ULL(23, 16) 164 #define ERDMA_CMD_HDR_WQEBB_INDEX_MASK GENMASK_ULL(15, 0) 165 166 struct erdma_cmdq_destroy_cq_req { 167 u64 hdr; 168 u32 cqn; 169 }; 170 171 #define ERDMA_EQ_TYPE_AEQ 0 172 #define ERDMA_EQ_TYPE_CEQ 1 173 174 struct erdma_cmdq_create_eq_req { 175 u64 hdr; 176 u64 qbuf_addr; 177 u8 vector_idx; 178 u8 eqn; 179 u8 depth; 180 u8 qtype; 181 u32 db_dma_addr_l; 182 u32 db_dma_addr_h; 183 }; 184 185 struct erdma_cmdq_destroy_eq_req { 186 u64 hdr; 187 u64 rsvd0; 188 u8 vector_idx; 189 u8 eqn; 190 u8 rsvd1; 191 u8 qtype; 192 }; 193 194 struct erdma_cmdq_config_mtu_req { 195 u64 hdr; 196 u32 mtu; 197 }; 198 199 /* create_cq cfg0 */ 200 #define ERDMA_CMD_CREATE_CQ_DEPTH_MASK GENMASK(31, 24) 201 #define ERDMA_CMD_CREATE_CQ_PAGESIZE_MASK GENMASK(23, 20) 202 #define ERDMA_CMD_CREATE_CQ_CQN_MASK GENMASK(19, 0) 203 204 /* create_cq cfg1 */ 205 #define ERDMA_CMD_CREATE_CQ_MTT_CNT_MASK GENMASK(31, 16) 206 #define ERDMA_CMD_CREATE_CQ_MTT_TYPE_MASK BIT(15) 207 #define ERDMA_CMD_CREATE_CQ_EQN_MASK GENMASK(9, 0) 208 209 struct erdma_cmdq_create_cq_req { 210 u64 hdr; 211 u32 cfg0; 212 u32 qbuf_addr_l; 213 u32 qbuf_addr_h; 214 u32 cfg1; 215 u64 cq_db_info_addr; 216 u32 first_page_offset; 217 }; 218 219 /* regmr/deregmr cfg0 */ 220 #define ERDMA_CMD_MR_VALID_MASK BIT(31) 221 #define ERDMA_CMD_MR_KEY_MASK GENMASK(27, 20) 222 #define ERDMA_CMD_MR_MPT_IDX_MASK GENMASK(19, 0) 223 224 /* regmr cfg1 */ 225 #define ERDMA_CMD_REGMR_PD_MASK GENMASK(31, 12) 226 #define ERDMA_CMD_REGMR_TYPE_MASK GENMASK(7, 6) 227 #define ERDMA_CMD_REGMR_RIGHT_MASK GENMASK(5, 2) 228 #define ERDMA_CMD_REGMR_ACC_MODE_MASK GENMASK(1, 0) 229 230 /* regmr cfg2 */ 231 #define ERDMA_CMD_REGMR_PAGESIZE_MASK GENMASK(31, 27) 232 #define ERDMA_CMD_REGMR_MTT_TYPE_MASK GENMASK(21, 20) 233 #define ERDMA_CMD_REGMR_MTT_CNT_MASK GENMASK(19, 0) 234 235 struct erdma_cmdq_reg_mr_req { 236 u64 hdr; 237 u32 cfg0; 238 u32 cfg1; 239 u64 start_va; 240 u32 size; 241 u32 cfg2; 242 u64 phy_addr[4]; 243 }; 244 245 struct erdma_cmdq_dereg_mr_req { 246 u64 hdr; 247 u32 cfg; 248 }; 249 250 /* modify qp cfg */ 251 #define ERDMA_CMD_MODIFY_QP_STATE_MASK GENMASK(31, 24) 252 #define ERDMA_CMD_MODIFY_QP_CC_MASK GENMASK(23, 20) 253 #define ERDMA_CMD_MODIFY_QP_QPN_MASK GENMASK(19, 0) 254 255 struct erdma_cmdq_modify_qp_req { 256 u64 hdr; 257 u32 cfg; 258 u32 cookie; 259 __be32 dip; 260 __be32 sip; 261 __be16 sport; 262 __be16 dport; 263 u32 send_nxt; 264 u32 recv_nxt; 265 }; 266 267 /* create qp cfg0 */ 268 #define ERDMA_CMD_CREATE_QP_SQ_DEPTH_MASK GENMASK(31, 20) 269 #define ERDMA_CMD_CREATE_QP_QPN_MASK GENMASK(19, 0) 270 271 /* create qp cfg1 */ 272 #define ERDMA_CMD_CREATE_QP_RQ_DEPTH_MASK GENMASK(31, 20) 273 #define ERDMA_CMD_CREATE_QP_PD_MASK GENMASK(19, 0) 274 275 /* create qp cqn_mtt_cfg */ 276 #define ERDMA_CMD_CREATE_QP_PAGE_SIZE_MASK GENMASK(31, 28) 277 #define ERDMA_CMD_CREATE_QP_CQN_MASK GENMASK(23, 0) 278 279 /* create qp mtt_cfg */ 280 #define ERDMA_CMD_CREATE_QP_PAGE_OFFSET_MASK GENMASK(31, 12) 281 #define ERDMA_CMD_CREATE_QP_MTT_CNT_MASK GENMASK(11, 1) 282 #define ERDMA_CMD_CREATE_QP_MTT_TYPE_MASK BIT(0) 283 284 #define ERDMA_CMDQ_CREATE_QP_RESP_COOKIE_MASK GENMASK_ULL(31, 0) 285 286 struct erdma_cmdq_create_qp_req { 287 u64 hdr; 288 u32 cfg0; 289 u32 cfg1; 290 u32 sq_cqn_mtt_cfg; 291 u32 rq_cqn_mtt_cfg; 292 u64 sq_buf_addr; 293 u64 rq_buf_addr; 294 u32 sq_mtt_cfg; 295 u32 rq_mtt_cfg; 296 u64 sq_db_info_dma_addr; 297 u64 rq_db_info_dma_addr; 298 }; 299 300 struct erdma_cmdq_destroy_qp_req { 301 u64 hdr; 302 u32 qpn; 303 }; 304 305 /* cap qword 0 definition */ 306 #define ERDMA_CMD_DEV_CAP_MAX_CQE_MASK GENMASK_ULL(47, 40) 307 #define ERDMA_CMD_DEV_CAP_MAX_RECV_WR_MASK GENMASK_ULL(23, 16) 308 #define ERDMA_CMD_DEV_CAP_MAX_MR_SIZE_MASK GENMASK_ULL(7, 0) 309 310 /* cap qword 1 definition */ 311 #define ERDMA_CMD_DEV_CAP_DMA_LOCAL_KEY_MASK GENMASK_ULL(63, 32) 312 #define ERDMA_CMD_DEV_CAP_DEFAULT_CC_MASK GENMASK_ULL(31, 28) 313 #define ERDMA_CMD_DEV_CAP_QBLOCK_MASK GENMASK_ULL(27, 16) 314 #define ERDMA_CMD_DEV_CAP_MAX_MW_MASK GENMASK_ULL(7, 0) 315 316 #define ERDMA_NQP_PER_QBLOCK 1024 317 318 #define ERDMA_CMD_INFO0_FW_VER_MASK GENMASK_ULL(31, 0) 319 320 /* CQE hdr */ 321 #define ERDMA_CQE_HDR_OWNER_MASK BIT(31) 322 #define ERDMA_CQE_HDR_OPCODE_MASK GENMASK(23, 16) 323 #define ERDMA_CQE_HDR_QTYPE_MASK GENMASK(15, 8) 324 #define ERDMA_CQE_HDR_SYNDROME_MASK GENMASK(7, 0) 325 326 #define ERDMA_CQE_QTYPE_SQ 0 327 #define ERDMA_CQE_QTYPE_RQ 1 328 #define ERDMA_CQE_QTYPE_CMDQ 2 329 330 struct erdma_cqe { 331 __be32 hdr; 332 __be32 qe_idx; 333 __be32 qpn; 334 union { 335 __le32 imm_data; 336 __be32 inv_rkey; 337 }; 338 __be32 size; 339 __be32 rsvd[3]; 340 }; 341 342 struct erdma_sge { 343 __aligned_le64 laddr; 344 __le32 length; 345 __le32 lkey; 346 }; 347 348 /* Receive Queue Element */ 349 struct erdma_rqe { 350 __le16 qe_idx; 351 __le16 rsvd0; 352 __le32 qpn; 353 __le32 rsvd1; 354 __le32 rsvd2; 355 __le64 to; 356 __le32 length; 357 __le32 stag; 358 }; 359 360 /* SQE */ 361 #define ERDMA_SQE_HDR_SGL_LEN_MASK GENMASK_ULL(63, 56) 362 #define ERDMA_SQE_HDR_WQEBB_CNT_MASK GENMASK_ULL(54, 52) 363 #define ERDMA_SQE_HDR_QPN_MASK GENMASK_ULL(51, 32) 364 #define ERDMA_SQE_HDR_OPCODE_MASK GENMASK_ULL(31, 27) 365 #define ERDMA_SQE_HDR_DWQE_MASK BIT_ULL(26) 366 #define ERDMA_SQE_HDR_INLINE_MASK BIT_ULL(25) 367 #define ERDMA_SQE_HDR_FENCE_MASK BIT_ULL(24) 368 #define ERDMA_SQE_HDR_SE_MASK BIT_ULL(23) 369 #define ERDMA_SQE_HDR_CE_MASK BIT_ULL(22) 370 #define ERDMA_SQE_HDR_WQEBB_INDEX_MASK GENMASK_ULL(15, 0) 371 372 /* REG MR attrs */ 373 #define ERDMA_SQE_MR_MODE_MASK GENMASK(1, 0) 374 #define ERDMA_SQE_MR_ACCESS_MASK GENMASK(5, 2) 375 #define ERDMA_SQE_MR_MTT_TYPE_MASK GENMASK(7, 6) 376 #define ERDMA_SQE_MR_MTT_CNT_MASK GENMASK(31, 12) 377 378 struct erdma_write_sqe { 379 __le64 hdr; 380 __be32 imm_data; 381 __le32 length; 382 383 __le32 sink_stag; 384 __le32 sink_to_l; 385 __le32 sink_to_h; 386 387 __le32 rsvd; 388 389 struct erdma_sge sgl[0]; 390 }; 391 392 struct erdma_send_sqe { 393 __le64 hdr; 394 union { 395 __be32 imm_data; 396 __le32 invalid_stag; 397 }; 398 399 __le32 length; 400 struct erdma_sge sgl[0]; 401 }; 402 403 struct erdma_readreq_sqe { 404 __le64 hdr; 405 __le32 invalid_stag; 406 __le32 length; 407 __le32 sink_stag; 408 __le32 sink_to_l; 409 __le32 sink_to_h; 410 __le32 rsvd; 411 }; 412 413 struct erdma_reg_mr_sqe { 414 __le64 hdr; 415 __le64 addr; 416 __le32 length; 417 __le32 stag; 418 __le32 attrs; 419 __le32 rsvd; 420 }; 421 422 /* EQ related. */ 423 #define ERDMA_DEFAULT_EQ_DEPTH 256 424 425 /* ceqe */ 426 #define ERDMA_CEQE_HDR_DB_MASK BIT_ULL(63) 427 #define ERDMA_CEQE_HDR_PI_MASK GENMASK_ULL(55, 32) 428 #define ERDMA_CEQE_HDR_O_MASK BIT_ULL(31) 429 #define ERDMA_CEQE_HDR_CQN_MASK GENMASK_ULL(19, 0) 430 431 /* aeqe */ 432 #define ERDMA_AEQE_HDR_O_MASK BIT(31) 433 #define ERDMA_AEQE_HDR_TYPE_MASK GENMASK(23, 16) 434 #define ERDMA_AEQE_HDR_SUBTYPE_MASK GENMASK(7, 0) 435 436 #define ERDMA_AE_TYPE_QP_FATAL_EVENT 0 437 #define ERDMA_AE_TYPE_QP_ERQ_ERR_EVENT 1 438 #define ERDMA_AE_TYPE_ACC_ERR_EVENT 2 439 #define ERDMA_AE_TYPE_CQ_ERR 3 440 #define ERDMA_AE_TYPE_OTHER_ERROR 4 441 442 struct erdma_aeqe { 443 __le32 hdr; 444 __le32 event_data0; 445 __le32 event_data1; 446 __le32 rsvd; 447 }; 448 449 enum erdma_opcode { 450 ERDMA_OP_WRITE = 0, 451 ERDMA_OP_READ = 1, 452 ERDMA_OP_SEND = 2, 453 ERDMA_OP_SEND_WITH_IMM = 3, 454 455 ERDMA_OP_RECEIVE = 4, 456 ERDMA_OP_RECV_IMM = 5, 457 ERDMA_OP_RECV_INV = 6, 458 459 ERDMA_OP_RSVD0 = 7, 460 ERDMA_OP_RSVD1 = 8, 461 ERDMA_OP_WRITE_WITH_IMM = 9, 462 463 ERDMA_OP_RSVD2 = 10, 464 ERDMA_OP_RSVD3 = 11, 465 466 ERDMA_OP_RSP_SEND_IMM = 12, 467 ERDMA_OP_SEND_WITH_INV = 13, 468 469 ERDMA_OP_REG_MR = 14, 470 ERDMA_OP_LOCAL_INV = 15, 471 ERDMA_OP_READ_WITH_INV = 16, 472 ERDMA_NUM_OPCODES = 17, 473 ERDMA_OP_INVALID = ERDMA_NUM_OPCODES + 1 474 }; 475 476 enum erdma_wc_status { 477 ERDMA_WC_SUCCESS = 0, 478 ERDMA_WC_GENERAL_ERR = 1, 479 ERDMA_WC_RECV_WQE_FORMAT_ERR = 2, 480 ERDMA_WC_RECV_STAG_INVALID_ERR = 3, 481 ERDMA_WC_RECV_ADDR_VIOLATION_ERR = 4, 482 ERDMA_WC_RECV_RIGHT_VIOLATION_ERR = 5, 483 ERDMA_WC_RECV_PDID_ERR = 6, 484 ERDMA_WC_RECV_WARRPING_ERR = 7, 485 ERDMA_WC_SEND_WQE_FORMAT_ERR = 8, 486 ERDMA_WC_SEND_WQE_ORD_EXCEED = 9, 487 ERDMA_WC_SEND_STAG_INVALID_ERR = 10, 488 ERDMA_WC_SEND_ADDR_VIOLATION_ERR = 11, 489 ERDMA_WC_SEND_RIGHT_VIOLATION_ERR = 12, 490 ERDMA_WC_SEND_PDID_ERR = 13, 491 ERDMA_WC_SEND_WARRPING_ERR = 14, 492 ERDMA_WC_FLUSH_ERR = 15, 493 ERDMA_WC_RETRY_EXC_ERR = 16, 494 ERDMA_NUM_WC_STATUS 495 }; 496 497 enum erdma_vendor_err { 498 ERDMA_WC_VENDOR_NO_ERR = 0, 499 ERDMA_WC_VENDOR_INVALID_RQE = 1, 500 ERDMA_WC_VENDOR_RQE_INVALID_STAG = 2, 501 ERDMA_WC_VENDOR_RQE_ADDR_VIOLATION = 3, 502 ERDMA_WC_VENDOR_RQE_ACCESS_RIGHT_ERR = 4, 503 ERDMA_WC_VENDOR_RQE_INVALID_PD = 5, 504 ERDMA_WC_VENDOR_RQE_WRAP_ERR = 6, 505 ERDMA_WC_VENDOR_INVALID_SQE = 0x20, 506 ERDMA_WC_VENDOR_ZERO_ORD = 0x21, 507 ERDMA_WC_VENDOR_SQE_INVALID_STAG = 0x30, 508 ERDMA_WC_VENDOR_SQE_ADDR_VIOLATION = 0x31, 509 ERDMA_WC_VENDOR_SQE_ACCESS_ERR = 0x32, 510 ERDMA_WC_VENDOR_SQE_INVALID_PD = 0x33, 511 ERDMA_WC_VENDOR_SQE_WARP_ERR = 0x34 512 }; 513 514 #endif 515