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Searched refs:ENABLE_CONTEXT (Results 1 – 25 of 28) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v1_0.c221 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_0_enable_system_domain()
264 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_0_setup_vmid_config()
Dgfxhub_v2_0.c259 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v2_0_enable_system_domain()
291 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v2_0_setup_vmid_config()
Dgfxhub_v3_0_3.c263 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v3_0_3_enable_system_domain()
301 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v3_0_3_setup_vmid_config()
Dgfxhub_v3_0.c260 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v3_0_enable_system_domain()
298 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v3_0_setup_vmid_config()
Dmmhub_v3_0_2.c279 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v3_0_2_enable_system_domain()
320 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in mmhub_v3_0_2_setup_vmid_config()
Dmmhub_v3_0_1.c280 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v3_0_1_enable_system_domain()
315 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in mmhub_v3_0_1_setup_vmid_config()
Dmmhub_v2_0.c330 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v2_0_enable_system_domain()
371 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in mmhub_v2_0_setup_vmid_config()
Dmmhub_v2_3.c254 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v2_3_enable_system_domain()
289 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in mmhub_v2_3_setup_vmid_config()
Dmmhub_v3_0.c286 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v3_0_enable_system_domain()
327 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in mmhub_v3_0_setup_vmid_config()
Dmmhub_v1_0.c202 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_0_enable_system_domain()
246 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_0_setup_vmid_config()
Dgfxhub_v2_1.c262 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v2_1_enable_system_domain()
300 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v2_1_setup_vmid_config()
Dgmc_v7_0.c663 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
693 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
Dmmhub_v1_7.c231 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_7_enable_system_domain()
278 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_7_setup_vmid_config()
Dgmc_v8_0.c902 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
932 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
Dmmhub_v9_4.c262 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v9_4_enable_system_domain()
313 ENABLE_CONTEXT, 1); in mmhub_v9_4_setup_vmid_config()
Dsid.h394 #define ENABLE_CONTEXT (1 << 0) macro
/linux-6.1.9/drivers/gpu/drm/radeon/
Drv770d.h635 #define ENABLE_CONTEXT (1 << 0) macro
Dnid.h128 #define ENABLE_CONTEXT (1 << 0) macro
Dni.c1298 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cayman_pcie_gart_enable()
1322 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cayman_pcie_gart_enable()
Dsid.h393 #define ENABLE_CONTEXT (1 << 0) macro
Dcikd.h511 #define ENABLE_CONTEXT (1 << 0) macro
Drv770.c940 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in rv770_pcie_gart_enable()
Devergreend.h1137 #define ENABLE_CONTEXT (1 << 0) macro
Dr600d.h574 #define ENABLE_CONTEXT (1 << 0) macro
Dsi.c4317 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in si_pcie_gart_enable()
4345 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in si_pcie_gart_enable()

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