1 /*
2 * Copyright © 2007-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #ifndef __DRM_EDID_H__
24 #define __DRM_EDID_H__
25
26 #include <linux/types.h>
27 #include <linux/hdmi.h>
28 #include <drm/drm_mode.h>
29
30 struct drm_device;
31 struct drm_edid;
32 struct i2c_adapter;
33
34 #define EDID_LENGTH 128
35 #define DDC_ADDR 0x50
36 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */
37
38 #define CEA_EXT 0x02
39 #define VTB_EXT 0x10
40 #define DI_EXT 0x40
41 #define LS_EXT 0x50
42 #define MI_EXT 0x60
43 #define DISPLAYID_EXT 0x70
44
45 struct est_timings {
46 u8 t1;
47 u8 t2;
48 u8 mfg_rsvd;
49 } __attribute__((packed));
50
51 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
52 #define EDID_TIMING_ASPECT_SHIFT 6
53 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
54
55 /* need to add 60 */
56 #define EDID_TIMING_VFREQ_SHIFT 0
57 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
58
59 struct std_timing {
60 u8 hsize; /* need to multiply by 8 then add 248 */
61 u8 vfreq_aspect;
62 } __attribute__((packed));
63
64 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
65 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
66 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
67 #define DRM_EDID_PT_STEREO (1 << 5)
68 #define DRM_EDID_PT_INTERLACED (1 << 7)
69
70 /* If detailed data is pixel timing */
71 struct detailed_pixel_timing {
72 u8 hactive_lo;
73 u8 hblank_lo;
74 u8 hactive_hblank_hi;
75 u8 vactive_lo;
76 u8 vblank_lo;
77 u8 vactive_vblank_hi;
78 u8 hsync_offset_lo;
79 u8 hsync_pulse_width_lo;
80 u8 vsync_offset_pulse_width_lo;
81 u8 hsync_vsync_offset_pulse_width_hi;
82 u8 width_mm_lo;
83 u8 height_mm_lo;
84 u8 width_height_mm_hi;
85 u8 hborder;
86 u8 vborder;
87 u8 misc;
88 } __attribute__((packed));
89
90 /* If it's not pixel timing, it'll be one of the below */
91 struct detailed_data_string {
92 u8 str[13];
93 } __attribute__((packed));
94
95 #define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << 0) /* 1.4 */
96 #define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << 1) /* 1.4 */
97 #define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << 2) /* 1.4 */
98 #define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */
99
100 #define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00
101 #define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01
102 #define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02
103 #define DRM_EDID_CVT_SUPPORT_FLAG 0x04
104
105 struct detailed_data_monitor_range {
106 u8 min_vfreq;
107 u8 max_vfreq;
108 u8 min_hfreq_khz;
109 u8 max_hfreq_khz;
110 u8 pixel_clock_mhz; /* need to multiply by 10 */
111 u8 flags;
112 union {
113 struct {
114 u8 reserved;
115 u8 hfreq_start_khz; /* need to multiply by 2 */
116 u8 c; /* need to divide by 2 */
117 __le16 m;
118 u8 k;
119 u8 j; /* need to divide by 2 */
120 } __attribute__((packed)) gtf2;
121 struct {
122 u8 version;
123 u8 data1; /* high 6 bits: extra clock resolution */
124 u8 data2; /* plus low 2 of above: max hactive */
125 u8 supported_aspects;
126 u8 flags; /* preferred aspect and blanking support */
127 u8 supported_scalings;
128 u8 preferred_refresh;
129 } __attribute__((packed)) cvt;
130 } __attribute__((packed)) formula;
131 } __attribute__((packed));
132
133 struct detailed_data_wpindex {
134 u8 white_yx_lo; /* Lower 2 bits each */
135 u8 white_x_hi;
136 u8 white_y_hi;
137 u8 gamma; /* need to divide by 100 then add 1 */
138 } __attribute__((packed));
139
140 struct detailed_data_color_point {
141 u8 windex1;
142 u8 wpindex1[3];
143 u8 windex2;
144 u8 wpindex2[3];
145 } __attribute__((packed));
146
147 struct cvt_timing {
148 u8 code[3];
149 } __attribute__((packed));
150
151 struct detailed_non_pixel {
152 u8 pad1;
153 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
154 fb=color point data, fa=standard timing data,
155 f9=undefined, f8=mfg. reserved */
156 u8 pad2;
157 union {
158 struct detailed_data_string str;
159 struct detailed_data_monitor_range range;
160 struct detailed_data_wpindex color;
161 struct std_timing timings[6];
162 struct cvt_timing cvt[4];
163 } __attribute__((packed)) data;
164 } __attribute__((packed));
165
166 #define EDID_DETAIL_EST_TIMINGS 0xf7
167 #define EDID_DETAIL_CVT_3BYTE 0xf8
168 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
169 #define EDID_DETAIL_STD_MODES 0xfa
170 #define EDID_DETAIL_MONITOR_CPDATA 0xfb
171 #define EDID_DETAIL_MONITOR_NAME 0xfc
172 #define EDID_DETAIL_MONITOR_RANGE 0xfd
173 #define EDID_DETAIL_MONITOR_STRING 0xfe
174 #define EDID_DETAIL_MONITOR_SERIAL 0xff
175
176 struct detailed_timing {
177 __le16 pixel_clock; /* need to multiply by 10 KHz */
178 union {
179 struct detailed_pixel_timing pixel_data;
180 struct detailed_non_pixel other_data;
181 } __attribute__((packed)) data;
182 } __attribute__((packed));
183
184 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
185 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
186 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
187 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
188 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
189 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
190 #define DRM_EDID_INPUT_DIGITAL (1 << 7)
191 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) /* 1.4 */
192 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) /* 1.4 */
193 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) /* 1.4 */
194 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) /* 1.4 */
195 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) /* 1.4 */
196 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) /* 1.4 */
197 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) /* 1.4 */
198 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) /* 1.4 */
199 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) /* 1.4 */
200 #define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0) /* 1.4 */
201 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0) /* 1.4 */
202 #define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0) /* 1.4 */
203 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0) /* 1.4 */
204 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0) /* 1.4 */
205 #define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0) /* 1.4 */
206 #define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */
207 #define DRM_EDID_DIGITAL_DFP_1_X (1 << 0) /* 1.3 */
208
209 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
210 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
211 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
212 /* If analog */
213 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
214 /* If digital */
215 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
216 #define DRM_EDID_FEATURE_RGB (0 << 3)
217 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
218 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
219 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
220
221 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
222 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
223 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
224
225 #define DRM_EDID_HDMI_DC_48 (1 << 6)
226 #define DRM_EDID_HDMI_DC_36 (1 << 5)
227 #define DRM_EDID_HDMI_DC_30 (1 << 4)
228 #define DRM_EDID_HDMI_DC_Y444 (1 << 3)
229
230 /* YCBCR 420 deep color modes */
231 #define DRM_EDID_YCBCR420_DC_48 (1 << 2)
232 #define DRM_EDID_YCBCR420_DC_36 (1 << 1)
233 #define DRM_EDID_YCBCR420_DC_30 (1 << 0)
234 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \
235 DRM_EDID_YCBCR420_DC_36 | \
236 DRM_EDID_YCBCR420_DC_30)
237
238 /* HDMI 2.1 additional fields */
239 #define DRM_EDID_MAX_FRL_RATE_MASK 0xf0
240 #define DRM_EDID_FAPA_START_LOCATION (1 << 0)
241 #define DRM_EDID_ALLM (1 << 1)
242 #define DRM_EDID_FVA (1 << 2)
243
244 /* Deep Color specific */
245 #define DRM_EDID_DC_30BIT_420 (1 << 0)
246 #define DRM_EDID_DC_36BIT_420 (1 << 1)
247 #define DRM_EDID_DC_48BIT_420 (1 << 2)
248
249 /* VRR specific */
250 #define DRM_EDID_CNMVRR (1 << 3)
251 #define DRM_EDID_CINEMA_VRR (1 << 4)
252 #define DRM_EDID_MDELTA (1 << 5)
253 #define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0
254 #define DRM_EDID_VRR_MAX_LOWER_MASK 0xff
255 #define DRM_EDID_VRR_MIN_MASK 0x3f
256
257 /* DSC specific */
258 #define DRM_EDID_DSC_10BPC (1 << 0)
259 #define DRM_EDID_DSC_12BPC (1 << 1)
260 #define DRM_EDID_DSC_16BPC (1 << 2)
261 #define DRM_EDID_DSC_ALL_BPP (1 << 3)
262 #define DRM_EDID_DSC_NATIVE_420 (1 << 6)
263 #define DRM_EDID_DSC_1P2 (1 << 7)
264 #define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0
265 #define DRM_EDID_DSC_MAX_SLICES 0xf
266 #define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f
267
268 /* ELD Header Block */
269 #define DRM_ELD_HEADER_BLOCK_SIZE 4
270
271 #define DRM_ELD_VER 0
272 # define DRM_ELD_VER_SHIFT 3
273 # define DRM_ELD_VER_MASK (0x1f << 3)
274 # define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */
275 # define DRM_ELD_VER_CANNED (0x1f << 3)
276
277 #define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */
278
279 /* ELD Baseline Block for ELD_Ver == 2 */
280 #define DRM_ELD_CEA_EDID_VER_MNL 4
281 # define DRM_ELD_CEA_EDID_VER_SHIFT 5
282 # define DRM_ELD_CEA_EDID_VER_MASK (7 << 5)
283 # define DRM_ELD_CEA_EDID_VER_NONE (0 << 5)
284 # define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5)
285 # define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5)
286 # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5)
287 # define DRM_ELD_MNL_SHIFT 0
288 # define DRM_ELD_MNL_MASK (0x1f << 0)
289
290 #define DRM_ELD_SAD_COUNT_CONN_TYPE 5
291 # define DRM_ELD_SAD_COUNT_SHIFT 4
292 # define DRM_ELD_SAD_COUNT_MASK (0xf << 4)
293 # define DRM_ELD_CONN_TYPE_SHIFT 2
294 # define DRM_ELD_CONN_TYPE_MASK (3 << 2)
295 # define DRM_ELD_CONN_TYPE_HDMI (0 << 2)
296 # define DRM_ELD_CONN_TYPE_DP (1 << 2)
297 # define DRM_ELD_SUPPORTS_AI (1 << 1)
298 # define DRM_ELD_SUPPORTS_HDCP (1 << 0)
299
300 #define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */
301 # define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */
302
303 #define DRM_ELD_SPEAKER 7
304 # define DRM_ELD_SPEAKER_MASK 0x7f
305 # define DRM_ELD_SPEAKER_RLRC (1 << 6)
306 # define DRM_ELD_SPEAKER_FLRC (1 << 5)
307 # define DRM_ELD_SPEAKER_RC (1 << 4)
308 # define DRM_ELD_SPEAKER_RLR (1 << 3)
309 # define DRM_ELD_SPEAKER_FC (1 << 2)
310 # define DRM_ELD_SPEAKER_LFE (1 << 1)
311 # define DRM_ELD_SPEAKER_FLR (1 << 0)
312
313 #define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */
314 # define DRM_ELD_PORT_ID_LEN 8
315
316 #define DRM_ELD_MANUFACTURER_NAME0 16
317 #define DRM_ELD_MANUFACTURER_NAME1 17
318
319 #define DRM_ELD_PRODUCT_CODE0 18
320 #define DRM_ELD_PRODUCT_CODE1 19
321
322 #define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */
323
324 #define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad))
325
326 struct edid {
327 u8 header[8];
328 /* Vendor & product info */
329 u8 mfg_id[2];
330 u8 prod_code[2];
331 u32 serial; /* FIXME: byte order */
332 u8 mfg_week;
333 u8 mfg_year;
334 /* EDID version */
335 u8 version;
336 u8 revision;
337 /* Display info: */
338 u8 input;
339 u8 width_cm;
340 u8 height_cm;
341 u8 gamma;
342 u8 features;
343 /* Color characteristics */
344 u8 red_green_lo;
345 u8 blue_white_lo;
346 u8 red_x;
347 u8 red_y;
348 u8 green_x;
349 u8 green_y;
350 u8 blue_x;
351 u8 blue_y;
352 u8 white_x;
353 u8 white_y;
354 /* Est. timings and mfg rsvd timings*/
355 struct est_timings established_timings;
356 /* Standard timings 1-8*/
357 struct std_timing standard_timings[8];
358 /* Detailing timings 1-4 */
359 struct detailed_timing detailed_timings[4];
360 /* Number of 128 byte ext. blocks */
361 u8 extensions;
362 /* Checksum */
363 u8 checksum;
364 } __attribute__((packed));
365
366 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
367
368 /* Short Audio Descriptor */
369 struct cea_sad {
370 u8 format;
371 u8 channels; /* max number of channels - 1 */
372 u8 freq;
373 u8 byte2; /* meaning depends on format */
374 };
375
376 struct drm_encoder;
377 struct drm_connector;
378 struct drm_connector_state;
379 struct drm_display_mode;
380
381 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads);
382 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb);
383 int drm_av_sync_delay(struct drm_connector *connector,
384 const struct drm_display_mode *mode);
385
386 #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
387 struct edid *drm_load_edid_firmware(struct drm_connector *connector);
388 int __drm_set_edid_firmware_path(const char *path);
389 int __drm_get_edid_firmware_path(char *buf, size_t bufsize);
390 #else
391 static inline struct edid *
drm_load_edid_firmware(struct drm_connector * connector)392 drm_load_edid_firmware(struct drm_connector *connector)
393 {
394 return ERR_PTR(-ENOENT);
395 }
396 #endif
397
398 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2);
399
400 int
401 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
402 const struct drm_connector *connector,
403 const struct drm_display_mode *mode);
404 int
405 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
406 const struct drm_connector *connector,
407 const struct drm_display_mode *mode);
408
409 void
410 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
411 const struct drm_connector *connector,
412 const struct drm_display_mode *mode,
413 enum hdmi_quantization_range rgb_quant_range);
414
415 /**
416 * drm_eld_mnl - Get ELD monitor name length in bytes.
417 * @eld: pointer to an eld memory structure with mnl set
418 */
drm_eld_mnl(const uint8_t * eld)419 static inline int drm_eld_mnl(const uint8_t *eld)
420 {
421 return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
422 }
423
424 /**
425 * drm_eld_sad - Get ELD SAD structures.
426 * @eld: pointer to an eld memory structure with sad_count set
427 */
drm_eld_sad(const uint8_t * eld)428 static inline const uint8_t *drm_eld_sad(const uint8_t *eld)
429 {
430 unsigned int ver, mnl;
431
432 ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT;
433 if (ver != 2 && ver != 31)
434 return NULL;
435
436 mnl = drm_eld_mnl(eld);
437 if (mnl > 16)
438 return NULL;
439
440 return eld + DRM_ELD_CEA_SAD(mnl, 0);
441 }
442
443 /**
444 * drm_eld_sad_count - Get ELD SAD count.
445 * @eld: pointer to an eld memory structure with sad_count set
446 */
drm_eld_sad_count(const uint8_t * eld)447 static inline int drm_eld_sad_count(const uint8_t *eld)
448 {
449 return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >>
450 DRM_ELD_SAD_COUNT_SHIFT;
451 }
452
453 /**
454 * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes
455 * @eld: pointer to an eld memory structure with mnl and sad_count set
456 *
457 * This is a helper for determining the payload size of the baseline block, in
458 * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block.
459 */
drm_eld_calc_baseline_block_size(const uint8_t * eld)460 static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld)
461 {
462 return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE +
463 drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3;
464 }
465
466 /**
467 * drm_eld_size - Get ELD size in bytes
468 * @eld: pointer to a complete eld memory structure
469 *
470 * The returned value does not include the vendor block. It's vendor specific,
471 * and comprises of the remaining bytes in the ELD memory buffer after
472 * drm_eld_size() bytes of header and baseline block.
473 *
474 * The returned value is guaranteed to be a multiple of 4.
475 */
drm_eld_size(const uint8_t * eld)476 static inline int drm_eld_size(const uint8_t *eld)
477 {
478 return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4;
479 }
480
481 /**
482 * drm_eld_get_spk_alloc - Get speaker allocation
483 * @eld: pointer to an ELD memory structure
484 *
485 * The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER
486 * field definitions to identify speakers.
487 */
drm_eld_get_spk_alloc(const uint8_t * eld)488 static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld)
489 {
490 return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK;
491 }
492
493 /**
494 * drm_eld_get_conn_type - Get device type hdmi/dp connected
495 * @eld: pointer to an ELD memory structure
496 *
497 * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to
498 * identify the display type connected.
499 */
drm_eld_get_conn_type(const uint8_t * eld)500 static inline u8 drm_eld_get_conn_type(const uint8_t *eld)
501 {
502 return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK;
503 }
504
505 /**
506 * drm_edid_decode_mfg_id - Decode the manufacturer ID
507 * @mfg_id: The manufacturer ID
508 * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0'
509 * termination
510 */
drm_edid_decode_mfg_id(u16 mfg_id,char vend[4])511 static inline const char *drm_edid_decode_mfg_id(u16 mfg_id, char vend[4])
512 {
513 vend[0] = '@' + ((mfg_id >> 10) & 0x1f);
514 vend[1] = '@' + ((mfg_id >> 5) & 0x1f);
515 vend[2] = '@' + ((mfg_id >> 0) & 0x1f);
516 vend[3] = '\0';
517
518 return vend;
519 }
520
521 /**
522 * drm_edid_encode_panel_id - Encode an ID for matching against drm_edid_get_panel_id()
523 * @vend_chr_0: First character of the vendor string.
524 * @vend_chr_1: Second character of the vendor string.
525 * @vend_chr_2: Third character of the vendor string.
526 * @product_id: The 16-bit product ID.
527 *
528 * This is a macro so that it can be calculated at compile time and used
529 * as an initializer.
530 *
531 * For instance:
532 * drm_edid_encode_panel_id('B', 'O', 'E', 0x2d08) => 0x09e52d08
533 *
534 * Return: a 32-bit ID per panel.
535 */
536 #define drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, product_id) \
537 ((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | \
538 (((u32)(vend_chr_1) - '@') & 0x1f) << 21 | \
539 (((u32)(vend_chr_2) - '@') & 0x1f) << 16 | \
540 ((product_id) & 0xffff))
541
542 /**
543 * drm_edid_decode_panel_id - Decode a panel ID from drm_edid_encode_panel_id()
544 * @panel_id: The panel ID to decode.
545 * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0'
546 * termination
547 * @product_id: The product ID will be returned here.
548 *
549 * For instance, after:
550 * drm_edid_decode_panel_id(0x09e52d08, vend, &product_id)
551 * These will be true:
552 * vend[0] = 'B'
553 * vend[1] = 'O'
554 * vend[2] = 'E'
555 * vend[3] = '\0'
556 * product_id = 0x2d08
557 */
drm_edid_decode_panel_id(u32 panel_id,char vend[4],u16 * product_id)558 static inline void drm_edid_decode_panel_id(u32 panel_id, char vend[4], u16 *product_id)
559 {
560 *product_id = (u16)(panel_id & 0xffff);
561 drm_edid_decode_mfg_id(panel_id >> 16, vend);
562 }
563
564 bool drm_probe_ddc(struct i2c_adapter *adapter);
565 struct edid *drm_do_get_edid(struct drm_connector *connector,
566 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
567 size_t len),
568 void *data);
569 struct edid *drm_get_edid(struct drm_connector *connector,
570 struct i2c_adapter *adapter);
571 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter);
572 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
573 struct i2c_adapter *adapter);
574 struct edid *drm_edid_duplicate(const struct edid *edid);
575 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);
576 int drm_add_override_edid_modes(struct drm_connector *connector);
577
578 u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
579 bool drm_detect_hdmi_monitor(const struct edid *edid);
580 bool drm_detect_monitor_audio(const struct edid *edid);
581 enum hdmi_quantization_range
582 drm_default_rgb_quant_range(const struct drm_display_mode *mode);
583 int drm_add_modes_noedid(struct drm_connector *connector,
584 int hdisplay, int vdisplay);
585 void drm_set_preferred_mode(struct drm_connector *connector,
586 int hpref, int vpref);
587
588 int drm_edid_header_is_valid(const void *edid);
589 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
590 bool *edid_corrupt);
591 bool drm_edid_is_valid(struct edid *edid);
592 void drm_edid_get_monitor_name(const struct edid *edid, char *name,
593 int buflen);
594 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
595 int hsize, int vsize, int fresh,
596 bool rb);
597 struct drm_display_mode *
598 drm_display_mode_from_cea_vic(struct drm_device *dev,
599 u8 video_code);
600
601 /* Interface based on struct drm_edid */
602 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size);
603 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid);
604 void drm_edid_free(const struct drm_edid *drm_edid);
605 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid);
606 const struct drm_edid *drm_edid_read(struct drm_connector *connector);
607 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
608 struct i2c_adapter *adapter);
609 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
610 int (*read_block)(void *context, u8 *buf, unsigned int block, size_t len),
611 void *context);
612 int drm_edid_connector_update(struct drm_connector *connector,
613 const struct drm_edid *edid);
614 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
615 int ext_id, int *ext_index);
616
617 #endif /* __DRM_EDID_H__ */
618