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Searched refs:DSPSURF (Results 1 – 8 of 8) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/i915/display/
Di9xx_plane.c493 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i9xx_plane_update_arm()
536 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); in i9xx_plane_disable_arm()
557 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in g4x_primary_async_flip()
1024 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; in i9xx_get_initial_plane_config()
1032 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; in i9xx_get_initial_plane_config()
Dintel_fbc.c363 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i965_fbc_nuke()
364 intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane))); in i965_fbc_nuke()
/linux-6.1.9/drivers/gpu/drm/i915/gvt/
Dfb_decoder.c248 plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_primary_plane()
Dhandlers.c1000 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
2268 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2271 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2274 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
Dcmd_parser.c1316 info->surf_reg = DSPSURF(info->pipe); in gen8_decode_mi_display_flip()
1382 info->surf_reg = DSPSURF(info->pipe); in skl_decode_mi_display_flip()
/linux-6.1.9/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c158 MMIO_D(DSPSURF(PIPE_A)); in iterate_generic_mmio()
167 MMIO_D(DSPSURF(PIPE_B)); in iterate_generic_mmio()
176 MMIO_D(DSPSURF(PIPE_C)); in iterate_generic_mmio()
Dintel_pm.c4120 …intel_uncore_write(&dev_priv->uncore, DSPSURF(pipe), intel_uncore_read(&dev_priv->uncore, DSPSURF(… in g4x_disable_trickle_feed()
4121 intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe)); in g4x_disable_trickle_feed()
Di915_reg.h4279 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) macro