Searched refs:DRAM (Results 1 – 25 of 92) sorted by relevance
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| /linux-6.1.9/Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 71 SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).
100 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
130 When the DRAM type is DDR3, this parameter defines the ODT disable
132 the ODT on the DRAM side and controller side are both disabled.
138 When the DRAM type is DDR3, this parameter defines the DRAM side drive
146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT
154 When the DRAM type is DDR3, this parameter defines the phy side CA line
162 When the DRAM type is DDR3, this parameter defines the PHY side DQ line
170 When the DRAM type is DDR3, this parameter defines the PHY side ODT
178 When the DRAM type is LPDDR3, this parameter defines then ODT disable
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| D | samsung,exynos5422-dmc.yaml | 17 DRAM memory chips are connected. The driver is to monitor the controller in
55 phandle of the connected DRAM memory device. For more information please
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| D | calxeda-ddr-ctrlr.yaml | 12 purposes and to learn about the DRAM topology.
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| /linux-6.1.9/Documentation/hid/ |
| D | amd-sfh-hid.rst | 60 on that allocates the DRAM address for each and every sensor and passes it to MP2-PCIe driver. On
72 2. Data transfer via DRAM.
77 the PCI layer. MP2 firmware writes the command output to the access DRAM memory which the client
78 layer has allocated. Firmware always writes minimum of 32 bytes into DRAM. So as a protocol driver
79 shall allocate minimum of 32 bytes DRAM space.
103 | | | Allocate the DRAM | Enable |
136 | | | Read the DRAM data for| | |
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| /linux-6.1.9/drivers/memory/tegra/ |
| D | Kconfig | 22 Tegra20 chips. The EMC controls the external DRAM on the board.
34 Tegra30 chips. The EMC controls the external DRAM on the board.
46 Tegra124 chips. The EMC controls the external DRAM on the board.
60 Tegra210 chips. The EMC controls the external DRAM on the board.
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| /linux-6.1.9/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-pll5-clk.yaml | 7 title: Allwinner A10 DRAM PLL
19 The first output is the DRAM clock output, the second is meant
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| /linux-6.1.9/sound/isa/gus/ |
| D | gus_dram.c | 28 outsb(GUSP(gus, DRAM), buffer, size1); in snd_gus_dram_poke()
64 insb(GUSP(gus, DRAM), buffer, size1); in snd_gus_dram_peek()
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| /linux-6.1.9/drivers/memory/samsung/ |
| D | Kconfig | 19 Frequency Scaling in DMC and DRAM. It also supports changing timings
20 of DRAM running with different frequency. The timings are calculated
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| /linux-6.1.9/Documentation/devicetree/bindings/firmware/ |
| D | nvidia,tegra210-bpmp.txt | 6 (suspend to ram), and also offloading DRAM memory clock scaling on
23 - #clock-cells : Should be 1 for platforms where DRAM clock control is
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| /linux-6.1.9/Documentation/devicetree/bindings/arm/sunxi/ |
| D | allwinner,sun4i-a10-mbus.yaml | 51 - description: DRAM controller/PHY registers
63 - description: DRAM controller/PHY module clock
64 - description: Register bus clock, shared by MBUS and DRAM
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| /linux-6.1.9/arch/arm/ |
| D | Kconfig-nommu | 14 hex '(S)DRAM Base Address' if SET_MEM_PARAM
18 hex '(S)DRAM SIZE' if SET_MEM_PARAM
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| /linux-6.1.9/Documentation/translations/zh_CN/mm/damon/ |
| D | index.rst | 19 - *准确度* （监测输出对DRAM级别的内存管理足够有用；但可能不适合CPU Cache级别），
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| /linux-6.1.9/Documentation/hwmon/ |
| D | asus_wmi_sensors.rst | 37 * DRAM Voltage,
48 * DRAM Voltage,
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| /linux-6.1.9/Documentation/devicetree/bindings/media/ |
| D | allwinner,sun4i-a10-csi.yaml | 39 - description: The CSI DRAM clock
44 - description: The CSI DRAM clock
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| D | allwinner,sun8i-h3-deinterlace.yaml | 39 - description: Deinterlace DRAM clock
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| /linux-6.1.9/arch/arm64/boot/dts/broadcom/stingray/ |
| D | stingray-board-base.dtsi | 22 &memory { /* Default DRAM banks */
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| /linux-6.1.9/arch/arm/mach-lpc32xx/ |
| D | suspend.S | 51 @ This guarantees a small windows where DRAM isn't busy
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| /linux-6.1.9/Documentation/arm/sa1100/ |
| D | lart.rst | 6 applications. It has 32 MB DRAM, 4MB Flash ROM, double RS232 and all
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| /linux-6.1.9/Documentation/devicetree/bindings/edac/ |
| D | dmc-520.yaml | 13 DMC-520 node is defined to describe DRAM error detection and correction.
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| /linux-6.1.9/Documentation/x86/ |
| D | amd-memory-encryption.rst | 12 automatically decrypted when read from DRAM and encrypted when written to
13 DRAM. SME can therefore be used to protect the contents of DRAM from physical
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| /linux-6.1.9/Documentation/admin-guide/perf/ |
| D | imx-ddr.rst | 5 There are no performance counters inside the DRAM controller, so performance
30 from different DRAM controller implementations, which is distinguished by quirks
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| /linux-6.1.9/Documentation/mm/damon/ |
| D | index.rst | 10 - *accurate* (the monitoring output is useful enough for DRAM level memory
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| /linux-6.1.9/arch/x86/ras/ |
| D | Kconfig | 13 have ECC DIMMs and doesn't have DRAM ECC checking enabled in the BIOS.
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| /linux-6.1.9/Documentation/driver-api/ |
| D | edac.rst | 18 The individual DRAM chips on a memory stick. These devices commonly
69 This is the name of the DRAM signal used to select the DRAM ranks to be
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| /linux-6.1.9/drivers/edac/ |
| D | Kconfig | 82 Support for error detection and correction of DRAM ECC errors on
91 Correctable errors into DRAM.
101 which trigger the DRAM ECC Read and Write respectively.
172 E3-1200 based DRAM controllers.
377 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
542 SoCs with ARM DMC-520 DRAM controller.
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