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Searched refs:DP_RECEIVER_CAP_SIZE (Results 1 – 24 of 24) sorted by relevance

/linux-6.1.9/include/drm/display/
Ddrm_dp_helper.h47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
107 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate() argument
113 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_lane_count() argument
119 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_enhanced_frame_cap() argument
126 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_fast_training_cap() argument
133 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_tps3_supported() argument
140 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_downspread() argument
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Ddrm_dp_mst_helper.h719 u8 dpcd[DP_RECEIVER_CAP_SIZE];
815 bool drm_dp_read_mst_cap(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
Ddrm_dp.h1521 #define DP_RECEIVER_CAP_SIZE 0xf macro
/linux-6.1.9/drivers/gpu/drm/display/
Ddrm_dp_helper.c284 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in __read_delay() argument
325 if (offset < DP_RECEIVER_CAP_SIZE) { in __read_delay()
339 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_clock_recovery_delay() argument
346 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_channel_eq_delay() argument
374 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_clock_recovery_delay() argument
398 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_channel_eq_delay() argument
769 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_is_type() argument
786 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_is_tmds() argument
873 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_downstream_port_count() argument
884 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_extended_dpcd_caps() argument
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Ddrm_dp_mst_topology.c3570 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_mst_cap() argument
4791 seq_printf(m, "dpcd: %*ph\n", DP_RECEIVER_CAP_SIZE, buf); in drm_dp_mst_dump_topology()
5825 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; in drm_dp_mst_dsc_aux_for_port()
/linux-6.1.9/drivers/gpu/drm/msm/dp/
Ddp_panel.c39 dpcd, (DP_RECEIVER_CAP_SIZE + 1)); in dp_panel_read_dpcd()
40 if (rlen < (DP_RECEIVER_CAP_SIZE + 1)) { in dp_panel_read_dpcd()
60 dpcd, (DP_RECEIVER_CAP_SIZE + 1)); in dp_panel_read_dpcd()
61 if (rlen < (DP_RECEIVER_CAP_SIZE + 1)) { in dp_panel_read_dpcd()
Ddp_panel.h39 u8 dpcd[DP_RECEIVER_CAP_SIZE + 1];
/linux-6.1.9/drivers/gpu/drm/rockchip/
Dcdn-dp-core.h103 u8 dpcd[DP_RECEIVER_CAP_SIZE];
Dcdn-dp-core.c379 DP_RECEIVER_CAP_SIZE); in cdn_dp_get_sink_capability()
/linux-6.1.9/drivers/gpu/drm/nouveau/
Dnouveau_encoder.h83 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Datombios_dp.c42 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
495 u8 dpcd[DP_RECEIVER_CAP_SIZE];
753 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); in amdgpu_atombios_dp_link_train()
Damdgpu_mode.h462 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/linux-6.1.9/drivers/gpu/drm/radeon/
Datombios_dp.c37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
545 u8 dpcd[DP_RECEIVER_CAP_SIZE];
841 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); in radeon_dp_link_train()
Dradeon_mode.h470 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/linux-6.1.9/drivers/gpu/drm/i915/display/
Dintel_dp_link_training.c47 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in intel_dp_read_lttpr_phy_caps() argument
70 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_read_lttpr_common_caps() argument
106 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_init_lttpr() argument
186 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in intel_dp_init_lttpr_and_dprx_caps()
Dintel_display_types.h1629 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/linux-6.1.9/drivers/gpu/drm/bridge/analogix/
Danalogix-anx6345.c64 u8 dpcd[DP_RECEIVER_CAP_SIZE];
135 &anx6345->dpcd, DP_RECEIVER_CAP_SIZE); in anx6345_dp_link_training()
Danalogix-anx78xx.c83 u8 dpcd[DP_RECEIVER_CAP_SIZE];
647 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE); in anx78xx_dp_link_training()
/linux-6.1.9/drivers/gpu/drm/tegra/
Ddp.c172 u8 dpcd[DP_RECEIVER_CAP_SIZE], value; in drm_dp_link_probe()
/linux-6.1.9/drivers/gpu/drm/bridge/cadence/
Dcdns-mhdp8546-core.c1385 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in cdns_mhdp_fill_sink_caps() argument
1410 u8 dpcd[DP_RECEIVER_CAP_SIZE], amp[2]; in cdns_mhdp_link_up()
1426 err = drm_dp_dpcd_read(&mhdp->aux, addr, dpcd, DP_RECEIVER_CAP_SIZE); in cdns_mhdp_link_up()
/linux-6.1.9/drivers/gpu/drm/bridge/
Dtc358767.c274 u8 dpcd[DP_RECEIVER_CAP_SIZE];
736 DP_RECEIVER_CAP_SIZE); in tc_get_display_props()
Dite-it6505.c427 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/linux-6.1.9/drivers/gpu/drm/xlnx/
Dzynqmp_dp.c318 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/linux-6.1.9/drivers/gpu/drm/mediatek/
Dmtk_dp.c105 u8 rx_cap[DP_RECEIVER_CAP_SIZE];