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Searched refs:DP_CONFIG (Results 1 – 8 of 8) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce/
Ddce_link_encoder.h54 SRI(DP_CONFIG, DP, id), \
88 SRI(DP_CONFIG, DP, id), \
163 uint32_t DP_CONFIG; member
Ddce_link_encoder.c604 REG_SET(DP_CONFIG, 0, in configure_encoder()
618 REG_SET(DP_CONFIG, 0, in dce60_configure_encoder()
/linux-6.1.9/drivers/mtd/nand/
Decc-mxic.c27 #define DP_CONFIG 0x00 macro
178 reg = readl(mxic->regs + DP_CONFIG); in mxic_ecc_disable_engine()
180 writel(reg, mxic->regs + DP_CONFIG); in mxic_ecc_disable_engine()
187 reg = readl(mxic->regs + DP_CONFIG); in mxic_ecc_enable_engine()
189 writel(reg, mxic->regs + DP_CONFIG); in mxic_ecc_enable_engine()
298 writel(ECC_TYP(idx), mxic->regs + DP_CONFIG); in mxic_ecc_init_ctx()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_dio_link_encoder.h37 SRI(DP_CONFIG, DP, id), \
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dio_link_encoder.h36 SRI(DP_CONFIG, DP, id), \
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_link_encoder.h47 SRI(DP_CONFIG, DP, id), \
88 uint32_t DP_CONFIG; member
Ddcn10_link_encoder.c492 REG_SET(DP_CONFIG, 0, in enc1_configure_encoder()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_resource.h295 SRI_ARR(TMDS_DCBALANCER_CONTROL, DIG, id), SRI_ARR(DP_CONFIG, DP, id), \