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Searched refs:DPU_DEBUG (Results 1 – 9 of 9) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_encoder_phys_wb.c89 DPU_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d is_rt:%d\n", in dpu_encoder_phys_wb_set_qos_remap()
250 DPU_DEBUG("[atomic_check:%d, \"%s\",%d,%d]\n", in dpu_encoder_phys_wb_atomic_check()
268 DPU_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id, in dpu_encoder_phys_wb_atomic_check()
307 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0); in _dpu_encoder_phys_wb_update_flush()
310 DPU_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0); in _dpu_encoder_phys_wb_update_flush()
324 DPU_DEBUG("Pending flush mask for CTL_%d is 0x%x, WB %d\n", in _dpu_encoder_phys_wb_update_flush()
340 DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n", in dpu_encoder_phys_wb_setup()
365 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0); in _dpu_encoder_phys_wb_frame_done_helper()
485 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0); in dpu_encoder_phys_wb_prepare_for_kickoff()
509 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0); in dpu_encoder_phys_wb_needs_single_flush()
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Ddpu_rm.c117 DPU_DEBUG("skip mixer %d without pingpong\n", lm->id); in dpu_rm_init()
177 DPU_DEBUG("skip intf %d with type none\n", i); in dpu_rm_init()
289 DPU_DEBUG("lm %d not peer of lm %d\n", peer_cfg->id, in _dpu_rm_check_lm_peer()
324 DPU_DEBUG("lm %d already reserved\n", lm_idx + LM_0); in _dpu_rm_check_lm_and_get_connected_blks()
336 DPU_DEBUG("lm %d pp %d already reserved\n", lm_cfg->id, in _dpu_rm_check_lm_and_get_connected_blks()
352 DPU_DEBUG("lm %d dspp %d already reserved\n", lm_cfg->id, in _dpu_rm_check_lm_and_get_connected_blks()
401 DPU_DEBUG("lm %d not peer of lm %d\n", LM_0 + j, in _dpu_rm_reserve_lms()
419 DPU_DEBUG("unable to find appropriate mixers\n"); in _dpu_rm_reserve_lms()
465 DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features); in _dpu_rm_reserve_ctls()
471 DPU_DEBUG("ctl %d match\n", j + CTL_0); in _dpu_rm_reserve_ctls()
Ddpu_kms.c126 DPU_DEBUG("plane:%d img:%dx%d ", in _dpu_plane_set_danger_state()
129 DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n", in _dpu_plane_set_danger_state()
137 DPU_DEBUG("Inactive plane:%d\n", plane->base.id); in _dpu_plane_set_danger_state()
155 DPU_DEBUG("Disabling danger:\n"); in _dpu_plane_danger_write()
160 DPU_DEBUG("Enabling danger:\n"); in _dpu_plane_danger_write()
502 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id); in dpu_kms_wait_for_commit_done()
507 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id); in dpu_kms_wait_for_commit_done()
777 DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n", in _dpu_kms_drm_obj_init()
1050 DPU_DEBUG("VBIF NRT is not defined"); in dpu_kms_hw_init()
1056 DPU_DEBUG("REG_DMA is not defined"); in dpu_kms_hw_init()
Ddpu_kms.h33 #define DPU_DEBUG(fmt, ...) \ macro
Ddpu_encoder_phys_cmd.c16 #define DPU_DEBUG_CMDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
769 DPU_DEBUG("intf %d\n", p->intf_idx - INTF_0); in dpu_encoder_phys_cmd_init()
Ddpu_core_perf.c529 DPU_DEBUG("optional max core clk rate, use default\n"); in dpu_core_perf_init()
Ddpu_encoder.c1930 DPU_DEBUG("invalid FB not kicking off\n"); in dpu_encoder_is_valid_for_commit()
2278 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); in dpu_encoder_setup_display()
2304 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n", in dpu_encoder_setup_display()
Ddpu_encoder_phys_vid.c14 #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
Ddpu_plane.c1532 DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, in dpu_plane_init()