| /linux-6.1.9/Documentation/devicetree/bindings/clock/ti/ |
| D | dpll.txt | 1 Binding for Texas Instruments DPLL clock.
6 register-mapped DPLL with usually two selectable input clocks
12 for the actual DPLL clock.
39 - reg : offsets for the register set for controlling the DPLL.
45 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
47 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
54 - DPLL mode setting - defining any one or more of the following overrides
56 - ti,low-power-stop : DPLL supports low power stop mode, gating output
57 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
58 - ti,lock : DPLL locks in programmed rate
[all …]
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| D | apll.txt | 11 a subtype of a DPLL [2], although a simplified one at that.
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| /linux-6.1.9/Documentation/devicetree/bindings/clock/ |
| D | microchip,sparx5-dpll.yaml | 7 title: Microchip Sparx5 DPLL Clock
13 The Sparx5 DPLL clock controller generates and supplies clock to
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| /linux-6.1.9/drivers/gpu/drm/i915/display/ |
| D | intel_dpll.c | 1568 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1569 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1572 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_enable_pll()
1584 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1589 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1590 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_enable_pll()
1720 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _vlv_enable_pll()
1721 intel_de_posting_read(dev_priv, DPLL(pipe)); in _vlv_enable_pll()
1724 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll()
1740 intel_de_write(dev_priv, DPLL(pipe), in vlv_enable_pll()
[all …]
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| D | intel_dvo.c | 466 dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); in intel_dvo_init()
467 intel_de_write(dev_priv, DPLL(pipe), in intel_dvo_init()
475 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); in intel_dvo_init()
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| D | intel_display_power_well.c | 1191 u32 val = intel_de_read(dev_priv, DPLL(pipe)); in vlv_display_power_well_init()
1197 intel_de_write(dev_priv, DPLL(pipe), val); in vlv_display_power_well_init()
1352 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
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| D | intel_display.c | 507 dpll_reg = DPLL(0); in vlv_wait_port_ready()
511 dpll_reg = DPLL(0); in vlv_wait_port_ready()
3298 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); in i9xx_get_pipe_config()
3309 DPLL(crtc->pipe)); in i9xx_get_pipe_config()
8864 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i830_enable_pipe()
8865 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe()
8868 intel_de_posting_read(dev_priv, DPLL(pipe)); in i830_enable_pipe()
8876 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe()
8880 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe()
8881 intel_de_posting_read(dev_priv, DPLL(pipe)); in i830_enable_pipe()
[all …]
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| D | intel_pps.c | 84 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
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| D | intel_display_power.c | 1737 u32 status = intel_de_read(dev_priv, DPLL(PIPE_A)); in chv_phy_control_init()
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| /linux-6.1.9/include/dt-bindings/clock/ |
| D | xlnx-zynqmp-clk.h | 15 #define DPLL 3 macro
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| /linux-6.1.9/arch/arm/mach-omap2/ |
| D | sleep24xx.S | 60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
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| /linux-6.1.9/arch/arm/boot/dts/ |
| D | exynos5422-odroid-core.dtsi | 97 /* derived from 600MHz DPLL */
199 /* derived from 600MHz DPLL */
235 /* derived from 600MHz DPLL */
247 /* derived from 600MHz DPLL */
262 /* derived from 600MHz DPLL */
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| D | rk3036.dtsi | 235 * Fix the emac parent clock is DPLL instead of APLL.
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| /linux-6.1.9/Documentation/devicetree/bindings/phy/ |
| D | ti-phy.txt | 10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
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| /linux-6.1.9/Documentation/arm/omap/ |
| D | dss.rst | 32 - Use DSI DPLL to create DSS FCK
301 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
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| /linux-6.1.9/drivers/net/wireless/realtek/rtlwifi/rtl8192se/ |
| D | reg.h | 256 #define DPLL 0x034A macro
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| /linux-6.1.9/Documentation/networking/device_drivers/hamradio/ |
| D | z8530drv.rst | 308 present at all (BayCom). It feeds back the output of the DPLL
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| /linux-6.1.9/drivers/gpu/drm/i915/ |
| D | i915_reg.h | 1474 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) macro
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