Home
last modified time | relevance | path

Searched refs:DPIO_CH0 (Results 1 – 7 of 7) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c1142 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1143 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1144 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1145 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1146 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1147 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1148 MMIO_D(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1149 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1150 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1151 MMIO_D(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
[all …]
/linux-6.1.9/drivers/gpu/drm/i915/display/
Dintel_display_power_well.c1317 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | in assert_chv_phy_status()
1318 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | in assert_chv_phy_status()
1319 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | in assert_chv_phy_status()
1325 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | in assert_chv_phy_status()
1326 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | in assert_chv_phy_status()
1327 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); in assert_chv_phy_status()
1333 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) in assert_chv_phy_status()
1334 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); in assert_chv_phy_status()
1341 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | in assert_chv_phy_status()
1343 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); in assert_chv_phy_status()
[all …]
Dintel_dpio_phy.c170 [DPIO_CH0] = { .port = PORT_B },
180 [DPIO_CH0] = { .port = PORT_A },
193 [DPIO_CH0] = { .port = PORT_B },
203 [DPIO_CH0] = { .port = PORT_A },
213 [DPIO_CH0] = { .port = PORT_C },
251 if (port == phy_info->channel[DPIO_CH0].port) { in bxt_port_to_phy_channel()
253 *ch = DPIO_CH0; in bxt_port_to_phy_channel()
268 *ch = DPIO_CH0; in bxt_port_to_phy_channel()
816 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_phy_pre_pll_enable()
831 if (ch == DPIO_CH0) in chv_phy_pre_pll_enable()
[all …]
Dintel_display_power.c1725 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | in chv_phy_control_init()
1727 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
1745 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); in chv_phy_control_init()
1748 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); in chv_phy_control_init()
1777 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
1780 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
Dintel_display_types.h1811 return DPIO_CH0; in vlv_dig_port_to_channel()
1841 return DPIO_CH0; in vlv_pipe_to_channel()
Dintel_display.h283 DPIO_CH0, enumerator
/linux-6.1.9/drivers/gpu/drm/i915/gvt/
Dhandlers.c534 enum dpio_channel ch = DPIO_CH0; in bxt_vgpu_get_dp_bitrate()
542 ch = DPIO_CH0; in bxt_vgpu_get_dp_bitrate()
546 ch = DPIO_CH0; in bxt_vgpu_get_dp_bitrate()
2759 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2761 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2767 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2769 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT, in init_bxt_mmio_info()