1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef DMUB_CMD_H
27 #define DMUB_CMD_H
28 
29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4)
30 #include "dmub_fw_types.h"
31 #include "include_legacy/atomfirmware.h"
32 
33 #if defined(_TEST_HARNESS)
34 #include <string.h>
35 #endif
36 #else
37 
38 #include <asm/byteorder.h>
39 #include <linux/types.h>
40 #include <linux/string.h>
41 #include <linux/delay.h>
42 
43 #include "atomfirmware.h"
44 
45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4)
46 
47 //<DMUB_TYPES>==================================================================
48 /* Basic type definitions. */
49 
50 #define __forceinline inline
51 
52 /**
53  * Flag from driver to indicate that ABM should be disabled gradually
54  * by slowly reversing all backlight programming and pixel compensation.
55  */
56 #define SET_ABM_PIPE_GRADUALLY_DISABLE           0
57 
58 /**
59  * Flag from driver to indicate that ABM should be disabled immediately
60  * and undo all backlight programming and pixel compensation.
61  */
62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE         255
63 
64 /**
65  * Flag from driver to indicate that ABM should be disabled immediately
66  * and keep the current backlight programming and pixel compensation.
67  */
68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
69 
70 /**
71  * Flag from driver to set the current ABM pipe index or ABM operating level.
72  */
73 #define SET_ABM_PIPE_NORMAL                      1
74 
75 /**
76  * Number of ambient light levels in ABM algorithm.
77  */
78 #define NUM_AMBI_LEVEL                  5
79 
80 /**
81  * Number of operating/aggression levels in ABM algorithm.
82  */
83 #define NUM_AGGR_LEVEL                  4
84 
85 /**
86  * Number of segments in the gamma curve.
87  */
88 #define NUM_POWER_FN_SEGS               8
89 
90 /**
91  * Number of segments in the backlight curve.
92  */
93 #define NUM_BL_CURVE_SEGS               16
94 
95 /* Maximum number of SubVP streams */
96 #define DMUB_MAX_SUBVP_STREAMS 2
97 
98 /* Maximum number of streams on any ASIC. */
99 #define DMUB_MAX_STREAMS 6
100 
101 /* Maximum number of planes on any ASIC. */
102 #define DMUB_MAX_PLANES 6
103 
104 /* Trace buffer offset for entry */
105 #define TRACE_BUFFER_ENTRY_OFFSET  16
106 
107 /**
108  * Maximum number of dirty rects supported by FW.
109  */
110 #define DMUB_MAX_DIRTY_RECTS 3
111 
112 /**
113  *
114  * PSR control version legacy
115  */
116 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
117 /**
118  * PSR control version with multi edp support
119  */
120 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
121 
122 
123 /**
124  * ABM control version legacy
125  */
126 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
127 
128 /**
129  * ABM control version with multi edp support
130  */
131 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
132 
133 /**
134  * Physical framebuffer address location, 64-bit.
135  */
136 #ifndef PHYSICAL_ADDRESS_LOC
137 #define PHYSICAL_ADDRESS_LOC union large_integer
138 #endif
139 
140 /**
141  * OS/FW agnostic memcpy
142  */
143 #ifndef dmub_memcpy
144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
145 #endif
146 
147 /**
148  * OS/FW agnostic memset
149  */
150 #ifndef dmub_memset
151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
152 #endif
153 
154 #if defined(__cplusplus)
155 extern "C" {
156 #endif
157 
158 /**
159  * OS/FW agnostic udelay
160  */
161 #ifndef dmub_udelay
162 #define dmub_udelay(microseconds) udelay(microseconds)
163 #endif
164 
165 /**
166  * union dmub_addr - DMUB physical/virtual 64-bit address.
167  */
168 union dmub_addr {
169 	struct {
170 		uint32_t low_part; /**< Lower 32 bits */
171 		uint32_t high_part; /**< Upper 32 bits */
172 	} u; /*<< Low/high bit access */
173 	uint64_t quad_part; /*<< 64 bit address */
174 };
175 
176 /**
177  * Dirty rect definition.
178  */
179 struct dmub_rect {
180 	/**
181 	 * Dirty rect x offset.
182 	 */
183 	uint32_t x;
184 
185 	/**
186 	 * Dirty rect y offset.
187 	 */
188 	uint32_t y;
189 
190 	/**
191 	 * Dirty rect width.
192 	 */
193 	uint32_t width;
194 
195 	/**
196 	 * Dirty rect height.
197 	 */
198 	uint32_t height;
199 };
200 
201 /**
202  * Flags that can be set by driver to change some PSR behaviour.
203  */
204 union dmub_psr_debug_flags {
205 	/**
206 	 * Debug flags.
207 	 */
208 	struct {
209 		/**
210 		 * Enable visual confirm in FW.
211 		 */
212 		uint32_t visual_confirm : 1;
213 
214 		/**
215 		 * Force all selective updates to bw full frame updates.
216 		 */
217 		uint32_t force_full_frame_update : 1;
218 
219 		/**
220 		 * Use HW Lock Mgr object to do HW locking in FW.
221 		 */
222 		uint32_t use_hw_lock_mgr : 1;
223 
224 		/**
225 		 * Use TPS3 signal when restore main link.
226 		 */
227 		uint32_t force_wakeup_by_tps3 : 1;
228 	} bitfields;
229 
230 	/**
231 	 * Union for debug flags.
232 	 */
233 	uint32_t u32All;
234 };
235 
236 /**
237  * DMUB visual confirm color
238  */
239 struct dmub_feature_caps {
240 	/**
241 	 * Max PSR version supported by FW.
242 	 */
243 	uint8_t psr;
244 	uint8_t fw_assisted_mclk_switch;
245 	uint8_t reserved[6];
246 };
247 
248 struct dmub_visual_confirm_color {
249 	/**
250 	 * Maximum 10 bits color value
251 	 */
252 	uint16_t color_r_cr;
253 	uint16_t color_g_y;
254 	uint16_t color_b_cb;
255 	uint16_t panel_inst;
256 };
257 
258 #if defined(__cplusplus)
259 }
260 #endif
261 
262 //==============================================================================
263 //</DMUB_TYPES>=================================================================
264 //==============================================================================
265 //< DMUB_META>==================================================================
266 //==============================================================================
267 #pragma pack(push, 1)
268 
269 /* Magic value for identifying dmub_fw_meta_info */
270 #define DMUB_FW_META_MAGIC 0x444D5542
271 
272 /* Offset from the end of the file to the dmub_fw_meta_info */
273 #define DMUB_FW_META_OFFSET 0x24
274 
275 /**
276  * struct dmub_fw_meta_info - metadata associated with fw binary
277  *
278  * NOTE: This should be considered a stable API. Fields should
279  *       not be repurposed or reordered. New fields should be
280  *       added instead to extend the structure.
281  *
282  * @magic_value: magic value identifying DMUB firmware meta info
283  * @fw_region_size: size of the firmware state region
284  * @trace_buffer_size: size of the tracebuffer region
285  * @fw_version: the firmware version information
286  * @dal_fw: 1 if the firmware is DAL
287  */
288 struct dmub_fw_meta_info {
289 	uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
290 	uint32_t fw_region_size; /**< size of the firmware state region */
291 	uint32_t trace_buffer_size; /**< size of the tracebuffer region */
292 	uint32_t fw_version; /**< the firmware version information */
293 	uint8_t dal_fw; /**< 1 if the firmware is DAL */
294 	uint8_t reserved[3]; /**< padding bits */
295 };
296 
297 /**
298  * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
299  */
300 union dmub_fw_meta {
301 	struct dmub_fw_meta_info info; /**< metadata info */
302 	uint8_t reserved[64]; /**< padding bits */
303 };
304 
305 #pragma pack(pop)
306 
307 //==============================================================================
308 //< DMUB Trace Buffer>================================================================
309 //==============================================================================
310 /**
311  * dmub_trace_code_t - firmware trace code, 32-bits
312  */
313 typedef uint32_t dmub_trace_code_t;
314 
315 /**
316  * struct dmcub_trace_buf_entry - Firmware trace entry
317  */
318 struct dmcub_trace_buf_entry {
319 	dmub_trace_code_t trace_code; /**< trace code for the event */
320 	uint32_t tick_count; /**< the tick count at time of trace */
321 	uint32_t param0; /**< trace defined parameter 0 */
322 	uint32_t param1; /**< trace defined parameter 1 */
323 };
324 
325 //==============================================================================
326 //< DMUB_STATUS>================================================================
327 //==============================================================================
328 
329 /**
330  * DMCUB scratch registers can be used to determine firmware status.
331  * Current scratch register usage is as follows:
332  *
333  * SCRATCH0: FW Boot Status register
334  * SCRATCH5: LVTMA Status Register
335  * SCRATCH15: FW Boot Options register
336  */
337 
338 /**
339  * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
340  */
341 union dmub_fw_boot_status {
342 	struct {
343 		uint32_t dal_fw : 1; /**< 1 if DAL FW */
344 		uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
345 		uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
346 		uint32_t restore_required : 1; /**< 1 if driver should call restore */
347 		uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
348 		uint32_t reserved : 1;
349 		uint32_t detection_required: 1; /**<  if detection need to be triggered by driver */
350 
351 	} bits; /**< status bits */
352 	uint32_t all; /**< 32-bit access to status bits */
353 };
354 
355 /**
356  * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
357  */
358 enum dmub_fw_boot_status_bit {
359 	DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
360 	DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
361 	DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
362 	DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
363 	DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
364 	DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
365 };
366 
367 /* Register bit definition for SCRATCH5 */
368 union dmub_lvtma_status {
369 	struct {
370 		uint32_t psp_ok : 1;
371 		uint32_t edp_on : 1;
372 		uint32_t reserved : 30;
373 	} bits;
374 	uint32_t all;
375 };
376 
377 enum dmub_lvtma_status_bit {
378 	DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
379 	DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
380 };
381 
382 /**
383  * union dmub_fw_boot_options - Boot option definitions for SCRATCH14
384  */
385 union dmub_fw_boot_options {
386 	struct {
387 		uint32_t pemu_env : 1; /**< 1 if PEMU */
388 		uint32_t fpga_env : 1; /**< 1 if FPGA */
389 		uint32_t optimized_init : 1; /**< 1 if optimized init */
390 		uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
391 		uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
392 		uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
393 		uint32_t z10_disable: 1; /**< 1 to disable z10 */
394 		uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
395 		uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
396 		uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */
397 		uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */
398 		/**< 1 if all root clock gating is enabled and low power memory is enabled*/
399 		uint32_t power_optimization: 1;
400 		uint32_t diag_env: 1; /* 1 if diagnostic environment */
401 		uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/
402 		uint32_t usb4_cm_version: 1; /**< 1 CM support */
403 		uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */
404 
405 		uint32_t reserved : 16; /**< reserved */
406 	} bits; /**< boot bits */
407 	uint32_t all; /**< 32-bit access to bits */
408 };
409 
410 enum dmub_fw_boot_options_bit {
411 	DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
412 	DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
413 	DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
414 };
415 
416 //==============================================================================
417 //</DMUB_STATUS>================================================================
418 //==============================================================================
419 //< DMUB_VBIOS>=================================================================
420 //==============================================================================
421 
422 /*
423  * enum dmub_cmd_vbios_type - VBIOS commands.
424  *
425  * Command IDs should be treated as stable ABI.
426  * Do not reuse or modify IDs.
427  */
428 enum dmub_cmd_vbios_type {
429 	/**
430 	 * Configures the DIG encoder.
431 	 */
432 	DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
433 	/**
434 	 * Controls the PHY.
435 	 */
436 	DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
437 	/**
438 	 * Sets the pixel clock/symbol clock.
439 	 */
440 	DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
441 	/**
442 	 * Enables or disables power gating.
443 	 */
444 	DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
445 	/**
446 	 * Controls embedded panels.
447 	 */
448 	DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
449 	/**
450 	 * Query DP alt status on a transmitter.
451 	 */
452 	DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT  = 26,
453 };
454 
455 //==============================================================================
456 //</DMUB_VBIOS>=================================================================
457 //==============================================================================
458 //< DMUB_GPINT>=================================================================
459 //==============================================================================
460 
461 /**
462  * The shifts and masks below may alternatively be used to format and read
463  * the command register bits.
464  */
465 
466 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
467 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
468 
469 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
470 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
471 
472 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
473 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
474 
475 /**
476  * Command responses.
477  */
478 
479 /**
480  * Return response for DMUB_GPINT__STOP_FW command.
481  */
482 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
483 
484 /**
485  * union dmub_gpint_data_register - Format for sending a command via the GPINT.
486  */
487 union dmub_gpint_data_register {
488 	struct {
489 		uint32_t param : 16; /**< 16-bit parameter */
490 		uint32_t command_code : 12; /**< GPINT command */
491 		uint32_t status : 4; /**< Command status bit */
492 	} bits; /**< GPINT bit access */
493 	uint32_t all; /**< GPINT  32-bit access */
494 };
495 
496 /*
497  * enum dmub_gpint_command - GPINT command to DMCUB FW
498  *
499  * Command IDs should be treated as stable ABI.
500  * Do not reuse or modify IDs.
501  */
502 enum dmub_gpint_command {
503 	/**
504 	 * Invalid command, ignored.
505 	 */
506 	DMUB_GPINT__INVALID_COMMAND = 0,
507 	/**
508 	 * DESC: Queries the firmware version.
509 	 * RETURN: Firmware version.
510 	 */
511 	DMUB_GPINT__GET_FW_VERSION = 1,
512 	/**
513 	 * DESC: Halts the firmware.
514 	 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
515 	 */
516 	DMUB_GPINT__STOP_FW = 2,
517 	/**
518 	 * DESC: Get PSR state from FW.
519 	 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
520 	 */
521 	DMUB_GPINT__GET_PSR_STATE = 7,
522 	/**
523 	 * DESC: Notifies DMCUB of the currently active streams.
524 	 * ARGS: Stream mask, 1 bit per active stream index.
525 	 */
526 	DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
527 	/**
528 	 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
529 	 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
530 	 *       By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
531 	 * RETURN: PSR residency in milli-percent.
532 	 */
533 	DMUB_GPINT__PSR_RESIDENCY = 9,
534 
535 	/**
536 	 * DESC: Notifies DMCUB detection is done so detection required can be cleared.
537 	 */
538 	DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
539 };
540 
541 /**
542  * INBOX0 generic command definition
543  */
544 union dmub_inbox0_cmd_common {
545 	struct {
546 		uint32_t command_code: 8; /**< INBOX0 command code */
547 		uint32_t param: 24; /**< 24-bit parameter */
548 	} bits;
549 	uint32_t all;
550 };
551 
552 /**
553  * INBOX0 hw_lock command definition
554  */
555 union dmub_inbox0_cmd_lock_hw {
556 	struct {
557 		uint32_t command_code: 8;
558 
559 		/* NOTE: Must be have enough bits to match: enum hw_lock_client */
560 		uint32_t hw_lock_client: 2;
561 
562 		/* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
563 		uint32_t otg_inst: 3;
564 		uint32_t opp_inst: 3;
565 		uint32_t dig_inst: 3;
566 
567 		/* NOTE: Below fields must match with: union dmub_hw_lock_flags */
568 		uint32_t lock_pipe: 1;
569 		uint32_t lock_cursor: 1;
570 		uint32_t lock_dig: 1;
571 		uint32_t triple_buffer_lock: 1;
572 
573 		uint32_t lock: 1;				/**< Lock */
574 		uint32_t should_release: 1;		/**< Release */
575 		uint32_t reserved: 7; 			/**< Reserved for extending more clients, HW, etc. */
576 	} bits;
577 	uint32_t all;
578 };
579 
580 union dmub_inbox0_data_register {
581 	union dmub_inbox0_cmd_common inbox0_cmd_common;
582 	union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
583 };
584 
585 enum dmub_inbox0_command {
586 	/**
587 	 * DESC: Invalid command, ignored.
588 	 */
589 	DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
590 	/**
591 	 * DESC: Notification to acquire/release HW lock
592 	 * ARGS:
593 	 */
594 	DMUB_INBOX0_CMD__HW_LOCK = 1,
595 };
596 //==============================================================================
597 //</DMUB_GPINT>=================================================================
598 //==============================================================================
599 //< DMUB_CMD>===================================================================
600 //==============================================================================
601 
602 /**
603  * Size in bytes of each DMUB command.
604  */
605 #define DMUB_RB_CMD_SIZE 64
606 
607 /**
608  * Maximum number of items in the DMUB ringbuffer.
609  */
610 #define DMUB_RB_MAX_ENTRY 128
611 
612 /**
613  * Ringbuffer size in bytes.
614  */
615 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
616 
617 /**
618  * REG_SET mask for reg offload.
619  */
620 #define REG_SET_MASK 0xFFFF
621 
622 /*
623  * enum dmub_cmd_type - DMUB inbox command.
624  *
625  * Command IDs should be treated as stable ABI.
626  * Do not reuse or modify IDs.
627  */
628 enum dmub_cmd_type {
629 	/**
630 	 * Invalid command.
631 	 */
632 	DMUB_CMD__NULL = 0,
633 	/**
634 	 * Read modify write register sequence offload.
635 	 */
636 	DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
637 	/**
638 	 * Field update register sequence offload.
639 	 */
640 	DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
641 	/**
642 	 * Burst write sequence offload.
643 	 */
644 	DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
645 	/**
646 	 * Reg wait sequence offload.
647 	 */
648 	DMUB_CMD__REG_REG_WAIT = 4,
649 	/**
650 	 * Workaround to avoid HUBP underflow during NV12 playback.
651 	 */
652 	DMUB_CMD__PLAT_54186_WA = 5,
653 	/**
654 	 * Command type used to query FW feature caps.
655 	 */
656 	DMUB_CMD__QUERY_FEATURE_CAPS = 6,
657 	/**
658 	 * Command type used to get visual confirm color.
659 	 */
660 	DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,
661 	/**
662 	 * Command type used for all PSR commands.
663 	 */
664 	DMUB_CMD__PSR = 64,
665 	/**
666 	 * Command type used for all MALL commands.
667 	 */
668 	DMUB_CMD__MALL = 65,
669 	/**
670 	 * Command type used for all ABM commands.
671 	 */
672 	DMUB_CMD__ABM = 66,
673 	/**
674 	 * Command type used to update dirty rects in FW.
675 	 */
676 	DMUB_CMD__UPDATE_DIRTY_RECT = 67,
677 	/**
678 	 * Command type used to update cursor info in FW.
679 	 */
680 	DMUB_CMD__UPDATE_CURSOR_INFO = 68,
681 	/**
682 	 * Command type used for HW locking in FW.
683 	 */
684 	DMUB_CMD__HW_LOCK = 69,
685 	/**
686 	 * Command type used to access DP AUX.
687 	 */
688 	DMUB_CMD__DP_AUX_ACCESS = 70,
689 	/**
690 	 * Command type used for OUTBOX1 notification enable
691 	 */
692 	DMUB_CMD__OUTBOX1_ENABLE = 71,
693 
694 	/**
695 	 * Command type used for all idle optimization commands.
696 	 */
697 	DMUB_CMD__IDLE_OPT = 72,
698 	/**
699 	 * Command type used for all clock manager commands.
700 	 */
701 	DMUB_CMD__CLK_MGR = 73,
702 	/**
703 	 * Command type used for all panel control commands.
704 	 */
705 	DMUB_CMD__PANEL_CNTL = 74,
706 	/**
707 	 * Command type used for <TODO:description>
708 	 */
709 	DMUB_CMD__CAB_FOR_SS = 75,
710 
711 	DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76,
712 
713 	/**
714 	 * Command type used for interfacing with DPIA.
715 	 */
716 	DMUB_CMD__DPIA = 77,
717 	/**
718 	 * Command type used for EDID CEA parsing
719 	 */
720 	DMUB_CMD__EDID_CEA = 79,
721 	/**
722 	 * Command type used for getting usbc cable ID
723 	 */
724 	DMUB_CMD_GET_USBC_CABLE_ID = 81,
725 	/**
726 	 * Command type used to query HPD state.
727 	 */
728 	DMUB_CMD__QUERY_HPD_STATE = 82,
729 	/**
730 	 * Command type used for all VBIOS interface commands.
731 	 */
732 
733 	/**
734 	 * Command type used to set DPIA HPD interrupt state
735 	 */
736 	DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,
737 
738 	DMUB_CMD__VBIOS = 128,
739 };
740 
741 /**
742  * enum dmub_out_cmd_type - DMUB outbox commands.
743  */
744 enum dmub_out_cmd_type {
745 	/**
746 	 * Invalid outbox command, ignored.
747 	 */
748 	DMUB_OUT_CMD__NULL = 0,
749 	/**
750 	 * Command type used for DP AUX Reply data notification
751 	 */
752 	DMUB_OUT_CMD__DP_AUX_REPLY = 1,
753 	/**
754 	 * Command type used for DP HPD event notification
755 	 */
756 	DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
757 	/**
758 	 * Command type used for SET_CONFIG Reply notification
759 	 */
760 	DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,
761 };
762 
763 /* DMUB_CMD__DPIA command sub-types. */
764 enum dmub_cmd_dpia_type {
765 	DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,
766 	DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1,
767 	DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2,
768 };
769 
770 #pragma pack(push, 1)
771 
772 /**
773  * struct dmub_cmd_header - Common command header fields.
774  */
775 struct dmub_cmd_header {
776 	unsigned int type : 8; /**< command type */
777 	unsigned int sub_type : 8; /**< command sub type */
778 	unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
779 	unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
780 	unsigned int reserved0 : 6; /**< reserved bits */
781 	unsigned int payload_bytes : 6;  /* payload excluding header - up to 60 bytes */
782 	unsigned int reserved1 : 2; /**< reserved bits */
783 };
784 
785 /*
786  * struct dmub_cmd_read_modify_write_sequence - Read modify write
787  *
788  * 60 payload bytes can hold up to 5 sets of read modify writes,
789  * each take 3 dwords.
790  *
791  * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
792  *
793  * modify_mask = 0xffff'ffff means all fields are going to be updated.  in this case
794  * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
795  */
796 struct dmub_cmd_read_modify_write_sequence {
797 	uint32_t addr; /**< register address */
798 	uint32_t modify_mask; /**< modify mask */
799 	uint32_t modify_value; /**< modify value */
800 };
801 
802 /**
803  * Maximum number of ops in read modify write sequence.
804  */
805 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
806 
807 /**
808  * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
809  */
810 struct dmub_rb_cmd_read_modify_write {
811 	struct dmub_cmd_header header;  /**< command header */
812 	/**
813 	 * Read modify write sequence.
814 	 */
815 	struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
816 };
817 
818 /*
819  * Update a register with specified masks and values sequeunce
820  *
821  * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
822  *
823  * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
824  *
825  *
826  * USE CASE:
827  *   1. auto-increment register where additional read would update pointer and produce wrong result
828  *   2. toggle a bit without read in the middle
829  */
830 
831 struct dmub_cmd_reg_field_update_sequence {
832 	uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
833 	uint32_t modify_value; /**< value to update with */
834 };
835 
836 /**
837  * Maximum number of ops in field update sequence.
838  */
839 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
840 
841 /**
842  * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
843  */
844 struct dmub_rb_cmd_reg_field_update_sequence {
845 	struct dmub_cmd_header header; /**< command header */
846 	uint32_t addr; /**< register address */
847 	/**
848 	 * Field update sequence.
849 	 */
850 	struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
851 };
852 
853 
854 /**
855  * Maximum number of burst write values.
856  */
857 #define DMUB_BURST_WRITE_VALUES__MAX  14
858 
859 /*
860  * struct dmub_rb_cmd_burst_write - Burst write
861  *
862  * support use case such as writing out LUTs.
863  *
864  * 60 payload bytes can hold up to 14 values to write to given address
865  *
866  * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
867  */
868 struct dmub_rb_cmd_burst_write {
869 	struct dmub_cmd_header header; /**< command header */
870 	uint32_t addr; /**< register start address */
871 	/**
872 	 * Burst write register values.
873 	 */
874 	uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
875 };
876 
877 /**
878  * struct dmub_rb_cmd_common - Common command header
879  */
880 struct dmub_rb_cmd_common {
881 	struct dmub_cmd_header header; /**< command header */
882 	/**
883 	 * Padding to RB_CMD_SIZE
884 	 */
885 	uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
886 };
887 
888 /**
889  * struct dmub_cmd_reg_wait_data - Register wait data
890  */
891 struct dmub_cmd_reg_wait_data {
892 	uint32_t addr; /**< Register address */
893 	uint32_t mask; /**< Mask for register bits */
894 	uint32_t condition_field_value; /**< Value to wait for */
895 	uint32_t time_out_us; /**< Time out for reg wait in microseconds */
896 };
897 
898 /**
899  * struct dmub_rb_cmd_reg_wait - Register wait command
900  */
901 struct dmub_rb_cmd_reg_wait {
902 	struct dmub_cmd_header header; /**< Command header */
903 	struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
904 };
905 
906 /**
907  * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
908  *
909  * Reprograms surface parameters to avoid underflow.
910  */
911 struct dmub_cmd_PLAT_54186_wa {
912 	uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
913 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
914 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
915 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
916 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
917 	struct {
918 		uint8_t hubp_inst : 4; /**< HUBP instance */
919 		uint8_t tmz_surface : 1; /**< TMZ enable or disable */
920 		uint8_t immediate :1; /**< Immediate flip */
921 		uint8_t vmid : 4; /**< VMID */
922 		uint8_t grph_stereo : 1; /**< 1 if stereo */
923 		uint32_t reserved : 21; /**< Reserved */
924 	} flip_params; /**< Pageflip parameters */
925 	uint32_t reserved[9]; /**< Reserved bits */
926 };
927 
928 /**
929  * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
930  */
931 struct dmub_rb_cmd_PLAT_54186_wa {
932 	struct dmub_cmd_header header; /**< Command header */
933 	struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
934 };
935 
936 /**
937  * struct dmub_rb_cmd_mall - MALL command data.
938  */
939 struct dmub_rb_cmd_mall {
940 	struct dmub_cmd_header header; /**< Common command header */
941 	union dmub_addr cursor_copy_src; /**< Cursor copy address */
942 	union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
943 	uint32_t tmr_delay; /**< Timer delay */
944 	uint32_t tmr_scale; /**< Timer scale */
945 	uint16_t cursor_width; /**< Cursor width in pixels */
946 	uint16_t cursor_pitch; /**< Cursor pitch in pixels */
947 	uint16_t cursor_height; /**< Cursor height in pixels */
948 	uint8_t cursor_bpp; /**< Cursor bits per pixel */
949 	uint8_t debug_bits; /**< Debug bits */
950 
951 	uint8_t reserved1; /**< Reserved bits */
952 	uint8_t reserved2; /**< Reserved bits */
953 };
954 
955 /**
956  * enum dmub_cmd_cab_type - TODO:
957  */
958 enum dmub_cmd_cab_type {
959 	DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,
960 	DMUB_CMD__CAB_NO_DCN_REQ = 1,
961 	DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,
962 };
963 
964 /**
965  * struct dmub_rb_cmd_cab_for_ss - TODO:
966  */
967 struct dmub_rb_cmd_cab_for_ss {
968 	struct dmub_cmd_header header;
969 	uint8_t cab_alloc_ways; /* total number of ways */
970 	uint8_t debug_bits;     /* debug bits */
971 };
972 
973 enum mclk_switch_mode {
974 	NONE = 0,
975 	FPO = 1,
976 	SUBVP = 2,
977 	VBLANK = 3,
978 };
979 
980 /* Per pipe struct which stores the MCLK switch mode
981  * data to be sent to DMUB.
982  * Named "v2" for now -- once FPO and SUBVP are fully merged
983  * the type name can be updated
984  */
985 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 {
986 	union {
987 		struct {
988 			uint32_t pix_clk_100hz;
989 			uint16_t main_vblank_start;
990 			uint16_t main_vblank_end;
991 			uint16_t mall_region_lines;
992 			uint16_t prefetch_lines;
993 			uint16_t prefetch_to_mall_start_lines;
994 			uint16_t processing_delay_lines;
995 			uint16_t htotal; // required to calculate line time for multi-display cases
996 			uint16_t vtotal;
997 			uint8_t main_pipe_index;
998 			uint8_t phantom_pipe_index;
999 			/* Since the microschedule is calculated in terms of OTG lines,
1000 			 * include any scaling factors to make sure when we get accurate
1001 			 * conversion when programming MALL_START_LINE (which is in terms
1002 			 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor
1003 			 * is 1/2 (numerator = 1, denominator = 2).
1004 			 */
1005 			uint8_t scale_factor_numerator;
1006 			uint8_t scale_factor_denominator;
1007 			uint8_t is_drr;
1008 			uint8_t main_split_pipe_index;
1009 			uint8_t phantom_split_pipe_index;
1010 		} subvp_data;
1011 
1012 		struct {
1013 			uint32_t pix_clk_100hz;
1014 			uint16_t vblank_start;
1015 			uint16_t vblank_end;
1016 			uint16_t vstartup_start;
1017 			uint16_t vtotal;
1018 			uint16_t htotal;
1019 			uint8_t vblank_pipe_index;
1020 			uint8_t padding[2];
1021 			struct {
1022 				uint8_t drr_in_use;
1023 				uint8_t drr_window_size_ms;	// Indicates largest VMIN/VMAX adjustment per frame
1024 				uint16_t min_vtotal_supported;	// Min VTOTAL that supports switching in VBLANK
1025 				uint16_t max_vtotal_supported;	// Max VTOTAL that can support SubVP static scheduling
1026 				uint8_t use_ramping;		// Use ramping or not
1027 			} drr_info;				// DRR considered as part of SubVP + VBLANK case
1028 		} vblank_data;
1029 	} pipe_config;
1030 
1031 	/* - subvp_data in the union (pipe_config) takes up 27 bytes.
1032 	 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only
1033 	 *   for the DMCUB command, cast to enum once we populate the DMCUB subvp state).
1034 	 */
1035 	uint8_t mode; // enum mclk_switch_mode
1036 };
1037 
1038 /**
1039  * Config data for Sub-VP and FPO
1040  * Named "v2" for now -- once FPO and SUBVP are fully merged
1041  * the type name can be updated
1042  */
1043 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 {
1044 	uint16_t watermark_a_cache;
1045 	uint8_t vertical_int_margin_us;
1046 	uint8_t pstate_allow_width_us;
1047 	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS];
1048 };
1049 
1050 /**
1051  * DMUB rb command definition for Sub-VP and FPO
1052  * Named "v2" for now -- once FPO and SUBVP are fully merged
1053  * the type name can be updated
1054  */
1055 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 {
1056 	struct dmub_cmd_header header;
1057 	struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data;
1058 };
1059 
1060 /**
1061  * enum dmub_cmd_idle_opt_type - Idle optimization command type.
1062  */
1063 enum dmub_cmd_idle_opt_type {
1064 	/**
1065 	 * DCN hardware restore.
1066 	 */
1067 	DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
1068 
1069 	/**
1070 	 * DCN hardware save.
1071 	 */
1072 	DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1
1073 };
1074 
1075 /**
1076  * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
1077  */
1078 struct dmub_rb_cmd_idle_opt_dcn_restore {
1079 	struct dmub_cmd_header header; /**< header */
1080 };
1081 
1082 /**
1083  * struct dmub_clocks - Clock update notification.
1084  */
1085 struct dmub_clocks {
1086 	uint32_t dispclk_khz; /**< dispclk kHz */
1087 	uint32_t dppclk_khz; /**< dppclk kHz */
1088 	uint32_t dcfclk_khz; /**< dcfclk kHz */
1089 	uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
1090 };
1091 
1092 /**
1093  * enum dmub_cmd_clk_mgr_type - Clock manager commands.
1094  */
1095 enum dmub_cmd_clk_mgr_type {
1096 	/**
1097 	 * Notify DMCUB of clock update.
1098 	 */
1099 	DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
1100 };
1101 
1102 /**
1103  * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
1104  */
1105 struct dmub_rb_cmd_clk_mgr_notify_clocks {
1106 	struct dmub_cmd_header header; /**< header */
1107 	struct dmub_clocks clocks; /**< clock data */
1108 };
1109 
1110 /**
1111  * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
1112  */
1113 struct dmub_cmd_digx_encoder_control_data {
1114 	union dig_encoder_control_parameters_v1_5 dig; /**< payload */
1115 };
1116 
1117 /**
1118  * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
1119  */
1120 struct dmub_rb_cmd_digx_encoder_control {
1121 	struct dmub_cmd_header header;  /**< header */
1122 	struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
1123 };
1124 
1125 /**
1126  * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
1127  */
1128 struct dmub_cmd_set_pixel_clock_data {
1129 	struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
1130 };
1131 
1132 /**
1133  * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
1134  */
1135 struct dmub_rb_cmd_set_pixel_clock {
1136 	struct dmub_cmd_header header; /**< header */
1137 	struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
1138 };
1139 
1140 /**
1141  * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
1142  */
1143 struct dmub_cmd_enable_disp_power_gating_data {
1144 	struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
1145 };
1146 
1147 /**
1148  * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
1149  */
1150 struct dmub_rb_cmd_enable_disp_power_gating {
1151 	struct dmub_cmd_header header; /**< header */
1152 	struct dmub_cmd_enable_disp_power_gating_data power_gating;  /**< payload */
1153 };
1154 
1155 /**
1156  * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
1157  */
1158 struct dmub_dig_transmitter_control_data_v1_7 {
1159 	uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
1160 	uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
1161 	union {
1162 		uint8_t digmode; /**< enum atom_encode_mode_def */
1163 		uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
1164 	} mode_laneset;
1165 	uint8_t lanenum; /**< Number of lanes */
1166 	union {
1167 		uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
1168 	} symclk_units;
1169 	uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
1170 	uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
1171 	uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
1172 	uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */
1173 	uint8_t reserved1; /**< For future use */
1174 	uint8_t reserved2[3]; /**< For future use */
1175 	uint32_t reserved3[11]; /**< For future use */
1176 };
1177 
1178 /**
1179  * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
1180  */
1181 union dmub_cmd_dig1_transmitter_control_data {
1182 	struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
1183 	struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7;  /**< payload 1.7 */
1184 };
1185 
1186 /**
1187  * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
1188  */
1189 struct dmub_rb_cmd_dig1_transmitter_control {
1190 	struct dmub_cmd_header header; /**< header */
1191 	union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
1192 };
1193 
1194 /**
1195  * DPIA tunnel command parameters.
1196  */
1197 struct dmub_cmd_dig_dpia_control_data {
1198 	uint8_t enc_id;         /** 0 = ENGINE_ID_DIGA, ... */
1199 	uint8_t action;         /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */
1200 	union {
1201 		uint8_t digmode;    /** enum atom_encode_mode_def */
1202 		uint8_t dplaneset;  /** DP voltage swing and pre-emphasis value */
1203 	} mode_laneset;
1204 	uint8_t lanenum;        /** Lane number 1, 2, 4, 8 */
1205 	uint32_t symclk_10khz;  /** Symbol Clock in 10Khz */
1206 	uint8_t hpdsel;         /** =0: HPD is not assigned */
1207 	uint8_t digfe_sel;      /** DIG stream( front-end ) selection, bit0 - DIG0 FE */
1208 	uint8_t dpia_id;        /** Index of DPIA */
1209 	uint8_t fec_rdy : 1;
1210 	uint8_t reserved : 7;
1211 	uint32_t reserved1;
1212 };
1213 
1214 /**
1215  * DMUB command for DPIA tunnel control.
1216  */
1217 struct dmub_rb_cmd_dig1_dpia_control {
1218 	struct dmub_cmd_header header;
1219 	struct dmub_cmd_dig_dpia_control_data dpia_control;
1220 };
1221 
1222 /**
1223  * SET_CONFIG Command Payload
1224  */
1225 struct set_config_cmd_payload {
1226 	uint8_t msg_type; /* set config message type */
1227 	uint8_t msg_data; /* set config message data */
1228 };
1229 
1230 /**
1231  * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
1232  */
1233 struct dmub_cmd_set_config_control_data {
1234 	struct set_config_cmd_payload cmd_pkt;
1235 	uint8_t instance; /* DPIA instance */
1236 	uint8_t immed_status; /* Immediate status returned in case of error */
1237 };
1238 
1239 /**
1240  * DMUB command structure for SET_CONFIG command.
1241  */
1242 struct dmub_rb_cmd_set_config_access {
1243 	struct dmub_cmd_header header; /* header */
1244 	struct dmub_cmd_set_config_control_data set_config_control; /* set config data */
1245 };
1246 
1247 /**
1248  * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
1249  */
1250 struct dmub_cmd_mst_alloc_slots_control_data {
1251 	uint8_t mst_alloc_slots; /* mst slots to be allotted */
1252 	uint8_t instance; /* DPIA instance */
1253 	uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */
1254 	uint8_t mst_slots_in_use; /* returns slots in use for error cases */
1255 };
1256 
1257 /**
1258  * DMUB command structure for SET_ command.
1259  */
1260 struct dmub_rb_cmd_set_mst_alloc_slots {
1261 	struct dmub_cmd_header header; /* header */
1262 	struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */
1263 };
1264 
1265 /**
1266  * DMUB command structure for DPIA HPD int enable control.
1267  */
1268 struct dmub_rb_cmd_dpia_hpd_int_enable {
1269 	struct dmub_cmd_header header; /* header */
1270 	uint32_t enable; /* dpia hpd interrupt enable */
1271 };
1272 
1273 /**
1274  * struct dmub_rb_cmd_dpphy_init - DPPHY init.
1275  */
1276 struct dmub_rb_cmd_dpphy_init {
1277 	struct dmub_cmd_header header; /**< header */
1278 	uint8_t reserved[60]; /**< reserved bits */
1279 };
1280 
1281 /**
1282  * enum dp_aux_request_action - DP AUX request command listing.
1283  *
1284  * 4 AUX request command bits are shifted to high nibble.
1285  */
1286 enum dp_aux_request_action {
1287 	/** I2C-over-AUX write request */
1288 	DP_AUX_REQ_ACTION_I2C_WRITE		= 0x00,
1289 	/** I2C-over-AUX read request */
1290 	DP_AUX_REQ_ACTION_I2C_READ		= 0x10,
1291 	/** I2C-over-AUX write status request */
1292 	DP_AUX_REQ_ACTION_I2C_STATUS_REQ	= 0x20,
1293 	/** I2C-over-AUX write request with MOT=1 */
1294 	DP_AUX_REQ_ACTION_I2C_WRITE_MOT		= 0x40,
1295 	/** I2C-over-AUX read request with MOT=1 */
1296 	DP_AUX_REQ_ACTION_I2C_READ_MOT		= 0x50,
1297 	/** I2C-over-AUX write status request with MOT=1 */
1298 	DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT	= 0x60,
1299 	/** Native AUX write request */
1300 	DP_AUX_REQ_ACTION_DPCD_WRITE		= 0x80,
1301 	/** Native AUX read request */
1302 	DP_AUX_REQ_ACTION_DPCD_READ		= 0x90
1303 };
1304 
1305 /**
1306  * enum aux_return_code_type - DP AUX process return code listing.
1307  */
1308 enum aux_return_code_type {
1309 	/** AUX process succeeded */
1310 	AUX_RET_SUCCESS = 0,
1311 	/** AUX process failed with unknown reason */
1312 	AUX_RET_ERROR_UNKNOWN,
1313 	/** AUX process completed with invalid reply */
1314 	AUX_RET_ERROR_INVALID_REPLY,
1315 	/** AUX process timed out */
1316 	AUX_RET_ERROR_TIMEOUT,
1317 	/** HPD was low during AUX process */
1318 	AUX_RET_ERROR_HPD_DISCON,
1319 	/** Failed to acquire AUX engine */
1320 	AUX_RET_ERROR_ENGINE_ACQUIRE,
1321 	/** AUX request not supported */
1322 	AUX_RET_ERROR_INVALID_OPERATION,
1323 	/** AUX process not available */
1324 	AUX_RET_ERROR_PROTOCOL_ERROR,
1325 };
1326 
1327 /**
1328  * enum aux_channel_type - DP AUX channel type listing.
1329  */
1330 enum aux_channel_type {
1331 	/** AUX thru Legacy DP AUX */
1332 	AUX_CHANNEL_LEGACY_DDC,
1333 	/** AUX thru DPIA DP tunneling */
1334 	AUX_CHANNEL_DPIA
1335 };
1336 
1337 /**
1338  * struct aux_transaction_parameters - DP AUX request transaction data
1339  */
1340 struct aux_transaction_parameters {
1341 	uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
1342 	uint8_t action; /**< enum dp_aux_request_action */
1343 	uint8_t length; /**< DP AUX request data length */
1344 	uint8_t reserved; /**< For future use */
1345 	uint32_t address; /**< DP AUX address */
1346 	uint8_t data[16]; /**< DP AUX write data */
1347 };
1348 
1349 /**
1350  * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1351  */
1352 struct dmub_cmd_dp_aux_control_data {
1353 	uint8_t instance; /**< AUX instance or DPIA instance */
1354 	uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
1355 	uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
1356 	uint8_t reserved0; /**< For future use */
1357 	uint16_t timeout; /**< timeout time in us */
1358 	uint16_t reserved1; /**< For future use */
1359 	enum aux_channel_type type; /**< enum aux_channel_type */
1360 	struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
1361 };
1362 
1363 /**
1364  * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
1365  */
1366 struct dmub_rb_cmd_dp_aux_access {
1367 	/**
1368 	 * Command header.
1369 	 */
1370 	struct dmub_cmd_header header;
1371 	/**
1372 	 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1373 	 */
1374 	struct dmub_cmd_dp_aux_control_data aux_control;
1375 };
1376 
1377 /**
1378  * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
1379  */
1380 struct dmub_rb_cmd_outbox1_enable {
1381 	/**
1382 	 * Command header.
1383 	 */
1384 	struct dmub_cmd_header header;
1385 	/**
1386 	 *  enable: 0x0 -> disable outbox1 notification (default value)
1387 	 *			0x1 -> enable outbox1 notification
1388 	 */
1389 	uint32_t enable;
1390 };
1391 
1392 /* DP AUX Reply command - OutBox Cmd */
1393 /**
1394  * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1395  */
1396 struct aux_reply_data {
1397 	/**
1398 	 * Aux cmd
1399 	 */
1400 	uint8_t command;
1401 	/**
1402 	 * Aux reply data length (max: 16 bytes)
1403 	 */
1404 	uint8_t length;
1405 	/**
1406 	 * Alignment only
1407 	 */
1408 	uint8_t pad[2];
1409 	/**
1410 	 * Aux reply data
1411 	 */
1412 	uint8_t data[16];
1413 };
1414 
1415 /**
1416  * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1417  */
1418 struct aux_reply_control_data {
1419 	/**
1420 	 * Reserved for future use
1421 	 */
1422 	uint32_t handle;
1423 	/**
1424 	 * Aux Instance
1425 	 */
1426 	uint8_t instance;
1427 	/**
1428 	 * Aux transaction result: definition in enum aux_return_code_type
1429 	 */
1430 	uint8_t result;
1431 	/**
1432 	 * Alignment only
1433 	 */
1434 	uint16_t pad;
1435 };
1436 
1437 /**
1438  * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
1439  */
1440 struct dmub_rb_cmd_dp_aux_reply {
1441 	/**
1442 	 * Command header.
1443 	 */
1444 	struct dmub_cmd_header header;
1445 	/**
1446 	 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1447 	 */
1448 	struct aux_reply_control_data control;
1449 	/**
1450 	 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1451 	 */
1452 	struct aux_reply_data reply_data;
1453 };
1454 
1455 /* DP HPD Notify command - OutBox Cmd */
1456 /**
1457  * DP HPD Type
1458  */
1459 enum dp_hpd_type {
1460 	/**
1461 	 * Normal DP HPD
1462 	 */
1463 	DP_HPD = 0,
1464 	/**
1465 	 * DP HPD short pulse
1466 	 */
1467 	DP_IRQ
1468 };
1469 
1470 /**
1471  * DP HPD Status
1472  */
1473 enum dp_hpd_status {
1474 	/**
1475 	 * DP_HPD status low
1476 	 */
1477 	DP_HPD_UNPLUG = 0,
1478 	/**
1479 	 * DP_HPD status high
1480 	 */
1481 	DP_HPD_PLUG
1482 };
1483 
1484 /**
1485  * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1486  */
1487 struct dp_hpd_data {
1488 	/**
1489 	 * DP HPD instance
1490 	 */
1491 	uint8_t instance;
1492 	/**
1493 	 * HPD type
1494 	 */
1495 	uint8_t hpd_type;
1496 	/**
1497 	 * HPD status: only for type: DP_HPD to indicate status
1498 	 */
1499 	uint8_t hpd_status;
1500 	/**
1501 	 * Alignment only
1502 	 */
1503 	uint8_t pad;
1504 };
1505 
1506 /**
1507  * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1508  */
1509 struct dmub_rb_cmd_dp_hpd_notify {
1510 	/**
1511 	 * Command header.
1512 	 */
1513 	struct dmub_cmd_header header;
1514 	/**
1515 	 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1516 	 */
1517 	struct dp_hpd_data hpd_data;
1518 };
1519 
1520 /**
1521  * Definition of a SET_CONFIG reply from DPOA.
1522  */
1523 enum set_config_status {
1524 	SET_CONFIG_PENDING = 0,
1525 	SET_CONFIG_ACK_RECEIVED,
1526 	SET_CONFIG_RX_TIMEOUT,
1527 	SET_CONFIG_UNKNOWN_ERROR,
1528 };
1529 
1530 /**
1531  * Definition of a set_config reply
1532  */
1533 struct set_config_reply_control_data {
1534 	uint8_t instance; /* DPIA Instance */
1535 	uint8_t status; /* Set Config reply */
1536 	uint16_t pad; /* Alignment */
1537 };
1538 
1539 /**
1540  * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command.
1541  */
1542 struct dmub_rb_cmd_dp_set_config_reply {
1543 	struct dmub_cmd_header header;
1544 	struct set_config_reply_control_data set_config_reply_control;
1545 };
1546 
1547 /**
1548  * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
1549  */
1550 struct dmub_cmd_hpd_state_query_data {
1551 	uint8_t instance; /**< HPD instance or DPIA instance */
1552 	uint8_t result; /**< For returning HPD state */
1553 	uint16_t pad; /** < Alignment */
1554 	enum aux_channel_type ch_type; /**< enum aux_channel_type */
1555 	enum aux_return_code_type status; /**< for returning the status of command */
1556 };
1557 
1558 /**
1559  * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
1560  */
1561 struct dmub_rb_cmd_query_hpd_state {
1562 	/**
1563 	 * Command header.
1564 	 */
1565 	struct dmub_cmd_header header;
1566 	/**
1567 	 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
1568 	 */
1569 	struct dmub_cmd_hpd_state_query_data data;
1570 };
1571 
1572 /*
1573  * Command IDs should be treated as stable ABI.
1574  * Do not reuse or modify IDs.
1575  */
1576 
1577 /**
1578  * PSR command sub-types.
1579  */
1580 enum dmub_cmd_psr_type {
1581 	/**
1582 	 * Set PSR version support.
1583 	 */
1584 	DMUB_CMD__PSR_SET_VERSION		= 0,
1585 	/**
1586 	 * Copy driver-calculated parameters to PSR state.
1587 	 */
1588 	DMUB_CMD__PSR_COPY_SETTINGS		= 1,
1589 	/**
1590 	 * Enable PSR.
1591 	 */
1592 	DMUB_CMD__PSR_ENABLE			= 2,
1593 
1594 	/**
1595 	 * Disable PSR.
1596 	 */
1597 	DMUB_CMD__PSR_DISABLE			= 3,
1598 
1599 	/**
1600 	 * Set PSR level.
1601 	 * PSR level is a 16-bit value dicated by driver that
1602 	 * will enable/disable different functionality.
1603 	 */
1604 	DMUB_CMD__PSR_SET_LEVEL			= 4,
1605 
1606 	/**
1607 	 * Forces PSR enabled until an explicit PSR disable call.
1608 	 */
1609 	DMUB_CMD__PSR_FORCE_STATIC		= 5,
1610 	/**
1611 	 * Set vtotal in psr active for FreeSync PSR.
1612 	 */
1613 	DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,
1614 	/**
1615 	 * Set PSR power option
1616 	 */
1617 	DMUB_CMD__SET_PSR_POWER_OPT = 7,
1618 };
1619 
1620 enum dmub_cmd_fams_type {
1621 	DMUB_CMD__FAMS_SETUP_FW_CTRL	= 0,
1622 	DMUB_CMD__FAMS_DRR_UPDATE		= 1,
1623 	DMUB_CMD__HANDLE_SUBVP_CMD	= 2, // specifically for SubVP cmd
1624 	/**
1625 	 * For SubVP set manual trigger in FW because it
1626 	 * triggers DRR_UPDATE_PENDING which SubVP relies
1627 	 * on (for any SubVP cases that use a DRR display)
1628 	 */
1629 	DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3,
1630 };
1631 
1632 /**
1633  * PSR versions.
1634  */
1635 enum psr_version {
1636 	/**
1637 	 * PSR version 1.
1638 	 */
1639 	PSR_VERSION_1				= 0,
1640 	/**
1641 	 * Freesync PSR SU.
1642 	 */
1643 	PSR_VERSION_SU_1			= 1,
1644 	/**
1645 	 * PSR not supported.
1646 	 */
1647 	PSR_VERSION_UNSUPPORTED			= 0xFFFFFFFF,
1648 };
1649 
1650 /**
1651  * enum dmub_cmd_mall_type - MALL commands
1652  */
1653 enum dmub_cmd_mall_type {
1654 	/**
1655 	 * Allows display refresh from MALL.
1656 	 */
1657 	DMUB_CMD__MALL_ACTION_ALLOW = 0,
1658 	/**
1659 	 * Disallows display refresh from MALL.
1660 	 */
1661 	DMUB_CMD__MALL_ACTION_DISALLOW = 1,
1662 	/**
1663 	 * Cursor copy for MALL.
1664 	 */
1665 	DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
1666 	/**
1667 	 * Controls DF requests.
1668 	 */
1669 	DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
1670 };
1671 
1672 /**
1673  * PHY Link rate for DP.
1674  */
1675 enum phy_link_rate {
1676 	/**
1677 	 * not supported.
1678 	 */
1679 	PHY_RATE_UNKNOWN = 0,
1680 	/**
1681 	 * Rate_1 (RBR)	- 1.62 Gbps/Lane
1682 	 */
1683 	PHY_RATE_162 = 1,
1684 	/**
1685 	 * Rate_2		- 2.16 Gbps/Lane
1686 	 */
1687 	PHY_RATE_216 = 2,
1688 	/**
1689 	 * Rate_3		- 2.43 Gbps/Lane
1690 	 */
1691 	PHY_RATE_243 = 3,
1692 	/**
1693 	 * Rate_4 (HBR)	- 2.70 Gbps/Lane
1694 	 */
1695 	PHY_RATE_270 = 4,
1696 	/**
1697 	 * Rate_5 (RBR2)- 3.24 Gbps/Lane
1698 	 */
1699 	PHY_RATE_324 = 5,
1700 	/**
1701 	 * Rate_6		- 4.32 Gbps/Lane
1702 	 */
1703 	PHY_RATE_432 = 6,
1704 	/**
1705 	 * Rate_7 (HBR2)- 5.40 Gbps/Lane
1706 	 */
1707 	PHY_RATE_540 = 7,
1708 	/**
1709 	 * Rate_8 (HBR3)- 8.10 Gbps/Lane
1710 	 */
1711 	PHY_RATE_810 = 8,
1712 	/**
1713 	 * UHBR10 - 10.0 Gbps/Lane
1714 	 */
1715 	PHY_RATE_1000 = 9,
1716 	/**
1717 	 * UHBR13.5 - 13.5 Gbps/Lane
1718 	 */
1719 	PHY_RATE_1350 = 10,
1720 	/**
1721 	 * UHBR10 - 20.0 Gbps/Lane
1722 	 */
1723 	PHY_RATE_2000 = 11,
1724 };
1725 
1726 /**
1727  * enum dmub_phy_fsm_state - PHY FSM states.
1728  * PHY FSM state to transit to during PSR enable/disable.
1729  */
1730 enum dmub_phy_fsm_state {
1731 	DMUB_PHY_FSM_POWER_UP_DEFAULT = 0,
1732 	DMUB_PHY_FSM_RESET,
1733 	DMUB_PHY_FSM_RESET_RELEASED,
1734 	DMUB_PHY_FSM_SRAM_LOAD_DONE,
1735 	DMUB_PHY_FSM_INITIALIZED,
1736 	DMUB_PHY_FSM_CALIBRATED,
1737 	DMUB_PHY_FSM_CALIBRATED_LP,
1738 	DMUB_PHY_FSM_CALIBRATED_PG,
1739 	DMUB_PHY_FSM_POWER_DOWN,
1740 	DMUB_PHY_FSM_PLL_EN,
1741 	DMUB_PHY_FSM_TX_EN,
1742 	DMUB_PHY_FSM_FAST_LP,
1743 };
1744 
1745 /**
1746  * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
1747  */
1748 struct dmub_cmd_psr_copy_settings_data {
1749 	/**
1750 	 * Flags that can be set by driver to change some PSR behaviour.
1751 	 */
1752 	union dmub_psr_debug_flags debug;
1753 	/**
1754 	 * 16-bit value dicated by driver that will enable/disable different functionality.
1755 	 */
1756 	uint16_t psr_level;
1757 	/**
1758 	 * DPP HW instance.
1759 	 */
1760 	uint8_t dpp_inst;
1761 	/**
1762 	 * MPCC HW instance.
1763 	 * Not used in dmub fw,
1764 	 * dmub fw will get active opp by reading odm registers.
1765 	 */
1766 	uint8_t mpcc_inst;
1767 	/**
1768 	 * OPP HW instance.
1769 	 * Not used in dmub fw,
1770 	 * dmub fw will get active opp by reading odm registers.
1771 	 */
1772 	uint8_t opp_inst;
1773 	/**
1774 	 * OTG HW instance.
1775 	 */
1776 	uint8_t otg_inst;
1777 	/**
1778 	 * DIG FE HW instance.
1779 	 */
1780 	uint8_t digfe_inst;
1781 	/**
1782 	 * DIG BE HW instance.
1783 	 */
1784 	uint8_t digbe_inst;
1785 	/**
1786 	 * DP PHY HW instance.
1787 	 */
1788 	uint8_t dpphy_inst;
1789 	/**
1790 	 * AUX HW instance.
1791 	 */
1792 	uint8_t aux_inst;
1793 	/**
1794 	 * Determines if SMU optimzations are enabled/disabled.
1795 	 */
1796 	uint8_t smu_optimizations_en;
1797 	/**
1798 	 * Unused.
1799 	 * TODO: Remove.
1800 	 */
1801 	uint8_t frame_delay;
1802 	/**
1803 	 * If RFB setup time is greater than the total VBLANK time,
1804 	 * it is not possible for the sink to capture the video frame
1805 	 * in the same frame the SDP is sent. In this case,
1806 	 * the frame capture indication bit should be set and an extra
1807 	 * static frame should be transmitted to the sink.
1808 	 */
1809 	uint8_t frame_cap_ind;
1810 	/**
1811 	 * Granularity of Y offset supported by sink.
1812 	 */
1813 	uint8_t su_y_granularity;
1814 	/**
1815 	 * Indicates whether sink should start capturing
1816 	 * immediately following active scan line,
1817 	 * or starting with the 2nd active scan line.
1818 	 */
1819 	uint8_t line_capture_indication;
1820 	/**
1821 	 * Multi-display optimizations are implemented on certain ASICs.
1822 	 */
1823 	uint8_t multi_disp_optimizations_en;
1824 	/**
1825 	 * The last possible line SDP may be transmitted without violating
1826 	 * the RFB setup time or entering the active video frame.
1827 	 */
1828 	uint16_t init_sdp_deadline;
1829 	/**
1830 	 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities
1831 	 */
1832 	uint8_t rate_control_caps ;
1833 	/*
1834 	 * Force PSRSU always doing full frame update
1835 	 */
1836 	uint8_t force_ffu_mode;
1837 	/**
1838 	 * Length of each horizontal line in us.
1839 	 */
1840 	uint32_t line_time_in_us;
1841 	/**
1842 	 * FEC enable status in driver
1843 	 */
1844 	uint8_t fec_enable_status;
1845 	/**
1846 	 * FEC re-enable delay when PSR exit.
1847 	 * unit is 100us, range form 0~255(0xFF).
1848 	 */
1849 	uint8_t fec_enable_delay_in100us;
1850 	/**
1851 	 * PSR control version.
1852 	 */
1853 	uint8_t cmd_version;
1854 	/**
1855 	 * Panel Instance.
1856 	 * Panel isntance to identify which psr_state to use
1857 	 * Currently the support is only for 0 or 1
1858 	 */
1859 	uint8_t panel_inst;
1860 	/*
1861 	 * DSC enable status in driver
1862 	 */
1863 	uint8_t dsc_enable_status;
1864 	/*
1865 	 * Use FSM state for PSR power up/down
1866 	 */
1867 	uint8_t use_phy_fsm;
1868 	/**
1869 	 * Explicit padding to 2 byte boundary.
1870 	 */
1871 	uint8_t pad3[2];
1872 };
1873 
1874 /**
1875  * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
1876  */
1877 struct dmub_rb_cmd_psr_copy_settings {
1878 	/**
1879 	 * Command header.
1880 	 */
1881 	struct dmub_cmd_header header;
1882 	/**
1883 	 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
1884 	 */
1885 	struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
1886 };
1887 
1888 /**
1889  * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
1890  */
1891 struct dmub_cmd_psr_set_level_data {
1892 	/**
1893 	 * 16-bit value dicated by driver that will enable/disable different functionality.
1894 	 */
1895 	uint16_t psr_level;
1896 	/**
1897 	 * PSR control version.
1898 	 */
1899 	uint8_t cmd_version;
1900 	/**
1901 	 * Panel Instance.
1902 	 * Panel isntance to identify which psr_state to use
1903 	 * Currently the support is only for 0 or 1
1904 	 */
1905 	uint8_t panel_inst;
1906 };
1907 
1908 /**
1909  * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
1910  */
1911 struct dmub_rb_cmd_psr_set_level {
1912 	/**
1913 	 * Command header.
1914 	 */
1915 	struct dmub_cmd_header header;
1916 	/**
1917 	 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
1918 	 */
1919 	struct dmub_cmd_psr_set_level_data psr_set_level_data;
1920 };
1921 
1922 struct dmub_rb_cmd_psr_enable_data {
1923 	/**
1924 	 * PSR control version.
1925 	 */
1926 	uint8_t cmd_version;
1927 	/**
1928 	 * Panel Instance.
1929 	 * Panel isntance to identify which psr_state to use
1930 	 * Currently the support is only for 0 or 1
1931 	 */
1932 	uint8_t panel_inst;
1933 	/**
1934 	 * Phy state to enter.
1935 	 * Values to use are defined in dmub_phy_fsm_state
1936 	 */
1937 	uint8_t phy_fsm_state;
1938 	/**
1939 	 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
1940 	 * Set this using enum phy_link_rate.
1941 	 * This does not support HDMI/DP2 for now.
1942 	 */
1943 	uint8_t phy_rate;
1944 };
1945 
1946 /**
1947  * Definition of a DMUB_CMD__PSR_ENABLE command.
1948  * PSR enable/disable is controlled using the sub_type.
1949  */
1950 struct dmub_rb_cmd_psr_enable {
1951 	/**
1952 	 * Command header.
1953 	 */
1954 	struct dmub_cmd_header header;
1955 
1956 	struct dmub_rb_cmd_psr_enable_data data;
1957 };
1958 
1959 /**
1960  * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
1961  */
1962 struct dmub_cmd_psr_set_version_data {
1963 	/**
1964 	 * PSR version that FW should implement.
1965 	 */
1966 	enum psr_version version;
1967 	/**
1968 	 * PSR control version.
1969 	 */
1970 	uint8_t cmd_version;
1971 	/**
1972 	 * Panel Instance.
1973 	 * Panel isntance to identify which psr_state to use
1974 	 * Currently the support is only for 0 or 1
1975 	 */
1976 	uint8_t panel_inst;
1977 	/**
1978 	 * Explicit padding to 4 byte boundary.
1979 	 */
1980 	uint8_t pad[2];
1981 };
1982 
1983 /**
1984  * Definition of a DMUB_CMD__PSR_SET_VERSION command.
1985  */
1986 struct dmub_rb_cmd_psr_set_version {
1987 	/**
1988 	 * Command header.
1989 	 */
1990 	struct dmub_cmd_header header;
1991 	/**
1992 	 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
1993 	 */
1994 	struct dmub_cmd_psr_set_version_data psr_set_version_data;
1995 };
1996 
1997 struct dmub_cmd_psr_force_static_data {
1998 	/**
1999 	 * PSR control version.
2000 	 */
2001 	uint8_t cmd_version;
2002 	/**
2003 	 * Panel Instance.
2004 	 * Panel isntance to identify which psr_state to use
2005 	 * Currently the support is only for 0 or 1
2006 	 */
2007 	uint8_t panel_inst;
2008 	/**
2009 	 * Explicit padding to 4 byte boundary.
2010 	 */
2011 	uint8_t pad[2];
2012 };
2013 
2014 /**
2015  * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
2016  */
2017 struct dmub_rb_cmd_psr_force_static {
2018 	/**
2019 	 * Command header.
2020 	 */
2021 	struct dmub_cmd_header header;
2022 	/**
2023 	 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
2024 	 */
2025 	struct dmub_cmd_psr_force_static_data psr_force_static_data;
2026 };
2027 
2028 /**
2029  * PSR SU debug flags.
2030  */
2031 union dmub_psr_su_debug_flags {
2032 	/**
2033 	 * PSR SU debug flags.
2034 	 */
2035 	struct {
2036 		/**
2037 		 * Update dirty rect in SW only.
2038 		 */
2039 		uint8_t update_dirty_rect_only : 1;
2040 		/**
2041 		 * Reset the cursor/plane state before processing the call.
2042 		 */
2043 		uint8_t reset_state : 1;
2044 	} bitfields;
2045 
2046 	/**
2047 	 * Union for debug flags.
2048 	 */
2049 	uint32_t u32All;
2050 };
2051 
2052 /**
2053  * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
2054  * This triggers a selective update for PSR SU.
2055  */
2056 struct dmub_cmd_update_dirty_rect_data {
2057 	/**
2058 	 * Dirty rects from OS.
2059 	 */
2060 	struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];
2061 	/**
2062 	 * PSR SU debug flags.
2063 	 */
2064 	union dmub_psr_su_debug_flags debug_flags;
2065 	/**
2066 	 * OTG HW instance.
2067 	 */
2068 	uint8_t pipe_idx;
2069 	/**
2070 	 * Number of dirty rects.
2071 	 */
2072 	uint8_t dirty_rect_count;
2073 	/**
2074 	 * PSR control version.
2075 	 */
2076 	uint8_t cmd_version;
2077 	/**
2078 	 * Panel Instance.
2079 	 * Panel isntance to identify which psr_state to use
2080 	 * Currently the support is only for 0 or 1
2081 	 */
2082 	uint8_t panel_inst;
2083 };
2084 
2085 /**
2086  * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
2087  */
2088 struct dmub_rb_cmd_update_dirty_rect {
2089 	/**
2090 	 * Command header.
2091 	 */
2092 	struct dmub_cmd_header header;
2093 	/**
2094 	 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
2095 	 */
2096 	struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;
2097 };
2098 
2099 /**
2100  * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
2101  */
2102 union dmub_reg_cursor_control_cfg {
2103 	struct {
2104 		uint32_t     cur_enable: 1;
2105 		uint32_t         reser0: 3;
2106 		uint32_t cur_2x_magnify: 1;
2107 		uint32_t         reser1: 3;
2108 		uint32_t           mode: 3;
2109 		uint32_t         reser2: 5;
2110 		uint32_t          pitch: 2;
2111 		uint32_t         reser3: 6;
2112 		uint32_t line_per_chunk: 5;
2113 		uint32_t         reser4: 3;
2114 	} bits;
2115 	uint32_t raw;
2116 };
2117 struct dmub_cursor_position_cache_hubp {
2118 	union dmub_reg_cursor_control_cfg cur_ctl;
2119 	union dmub_reg_position_cfg {
2120 		struct {
2121 			uint32_t cur_x_pos: 16;
2122 			uint32_t cur_y_pos: 16;
2123 		} bits;
2124 		uint32_t raw;
2125 	} position;
2126 	union dmub_reg_hot_spot_cfg {
2127 		struct {
2128 			uint32_t hot_x: 16;
2129 			uint32_t hot_y: 16;
2130 		} bits;
2131 		uint32_t raw;
2132 	} hot_spot;
2133 	union dmub_reg_dst_offset_cfg {
2134 		struct {
2135 			uint32_t dst_x_offset: 13;
2136 			uint32_t reserved: 19;
2137 		} bits;
2138 		uint32_t raw;
2139 	} dst_offset;
2140 };
2141 
2142 union dmub_reg_cur0_control_cfg {
2143 	struct {
2144 		uint32_t     cur0_enable: 1;
2145 		uint32_t  expansion_mode: 1;
2146 		uint32_t          reser0: 1;
2147 		uint32_t     cur0_rom_en: 1;
2148 		uint32_t            mode: 3;
2149 		uint32_t        reserved: 25;
2150 	} bits;
2151 	uint32_t raw;
2152 };
2153 struct dmub_cursor_position_cache_dpp {
2154 	union dmub_reg_cur0_control_cfg cur0_ctl;
2155 };
2156 struct dmub_cursor_position_cfg {
2157 	struct  dmub_cursor_position_cache_hubp pHubp;
2158 	struct  dmub_cursor_position_cache_dpp  pDpp;
2159 	uint8_t pipe_idx;
2160 	/*
2161 	 * Padding is required. To be 4 Bytes Aligned.
2162 	 */
2163 	uint8_t padding[3];
2164 };
2165 
2166 struct dmub_cursor_attribute_cache_hubp {
2167 	uint32_t SURFACE_ADDR_HIGH;
2168 	uint32_t SURFACE_ADDR;
2169 	union    dmub_reg_cursor_control_cfg  cur_ctl;
2170 	union    dmub_reg_cursor_size_cfg {
2171 		struct {
2172 			uint32_t width: 16;
2173 			uint32_t height: 16;
2174 		} bits;
2175 		uint32_t raw;
2176 	} size;
2177 	union    dmub_reg_cursor_settings_cfg {
2178 		struct {
2179 			uint32_t     dst_y_offset: 8;
2180 			uint32_t chunk_hdl_adjust: 2;
2181 			uint32_t         reserved: 22;
2182 		} bits;
2183 		uint32_t raw;
2184 	} settings;
2185 };
2186 struct dmub_cursor_attribute_cache_dpp {
2187 	union dmub_reg_cur0_control_cfg cur0_ctl;
2188 };
2189 struct dmub_cursor_attributes_cfg {
2190 	struct  dmub_cursor_attribute_cache_hubp aHubp;
2191 	struct  dmub_cursor_attribute_cache_dpp  aDpp;
2192 };
2193 
2194 struct dmub_cmd_update_cursor_payload0 {
2195 	/**
2196 	 * Cursor dirty rects.
2197 	 */
2198 	struct dmub_rect cursor_rect;
2199 	/**
2200 	 * PSR SU debug flags.
2201 	 */
2202 	union dmub_psr_su_debug_flags debug_flags;
2203 	/**
2204 	 * Cursor enable/disable.
2205 	 */
2206 	uint8_t enable;
2207 	/**
2208 	 * OTG HW instance.
2209 	 */
2210 	uint8_t pipe_idx;
2211 	/**
2212 	 * PSR control version.
2213 	 */
2214 	uint8_t cmd_version;
2215 	/**
2216 	 * Panel Instance.
2217 	 * Panel isntance to identify which psr_state to use
2218 	 * Currently the support is only for 0 or 1
2219 	 */
2220 	uint8_t panel_inst;
2221 	/**
2222 	 * Cursor Position Register.
2223 	 * Registers contains Hubp & Dpp modules
2224 	 */
2225 	struct dmub_cursor_position_cfg position_cfg;
2226 };
2227 
2228 struct dmub_cmd_update_cursor_payload1 {
2229 	struct dmub_cursor_attributes_cfg attribute_cfg;
2230 };
2231 
2232 union dmub_cmd_update_cursor_info_data {
2233 	struct dmub_cmd_update_cursor_payload0 payload0;
2234 	struct dmub_cmd_update_cursor_payload1 payload1;
2235 };
2236 /**
2237  * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
2238  */
2239 struct dmub_rb_cmd_update_cursor_info {
2240 	/**
2241 	 * Command header.
2242 	 */
2243 	struct dmub_cmd_header header;
2244 	/**
2245 	 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
2246 	 */
2247 	union dmub_cmd_update_cursor_info_data update_cursor_info_data;
2248 };
2249 
2250 /**
2251  * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2252  */
2253 struct dmub_cmd_psr_set_vtotal_data {
2254 	/**
2255 	 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..
2256 	 */
2257 	uint16_t psr_vtotal_idle;
2258 	/**
2259 	 * PSR control version.
2260 	 */
2261 	uint8_t cmd_version;
2262 	/**
2263 	 * Panel Instance.
2264 	 * Panel isntance to identify which psr_state to use
2265 	 * Currently the support is only for 0 or 1
2266 	 */
2267 	uint8_t panel_inst;
2268 	/*
2269 	 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.
2270 	 */
2271 	uint16_t psr_vtotal_su;
2272 	/**
2273 	 * Explicit padding to 4 byte boundary.
2274 	 */
2275 	uint8_t pad2[2];
2276 };
2277 
2278 /**
2279  * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2280  */
2281 struct dmub_rb_cmd_psr_set_vtotal {
2282 	/**
2283 	 * Command header.
2284 	 */
2285 	struct dmub_cmd_header header;
2286 	/**
2287 	 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2288 	 */
2289 	struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;
2290 };
2291 
2292 /**
2293  * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.
2294  */
2295 struct dmub_cmd_psr_set_power_opt_data {
2296 	/**
2297 	 * PSR control version.
2298 	 */
2299 	uint8_t cmd_version;
2300 	/**
2301 	 * Panel Instance.
2302 	 * Panel isntance to identify which psr_state to use
2303 	 * Currently the support is only for 0 or 1
2304 	 */
2305 	uint8_t panel_inst;
2306 	/**
2307 	 * Explicit padding to 4 byte boundary.
2308 	 */
2309 	uint8_t pad[2];
2310 	/**
2311 	 * PSR power option
2312 	 */
2313 	uint32_t power_opt;
2314 };
2315 
2316 /**
2317  * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
2318  */
2319 struct dmub_rb_cmd_psr_set_power_opt {
2320 	/**
2321 	 * Command header.
2322 	 */
2323 	struct dmub_cmd_header header;
2324 	/**
2325 	 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
2326 	 */
2327 	struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
2328 };
2329 
2330 /**
2331  * Set of HW components that can be locked.
2332  *
2333  * Note: If updating with more HW components, fields
2334  * in dmub_inbox0_cmd_lock_hw must be updated to match.
2335  */
2336 union dmub_hw_lock_flags {
2337 	/**
2338 	 * Set of HW components that can be locked.
2339 	 */
2340 	struct {
2341 		/**
2342 		 * Lock/unlock OTG master update lock.
2343 		 */
2344 		uint8_t lock_pipe   : 1;
2345 		/**
2346 		 * Lock/unlock cursor.
2347 		 */
2348 		uint8_t lock_cursor : 1;
2349 		/**
2350 		 * Lock/unlock global update lock.
2351 		 */
2352 		uint8_t lock_dig    : 1;
2353 		/**
2354 		 * Triple buffer lock requires additional hw programming to usual OTG master lock.
2355 		 */
2356 		uint8_t triple_buffer_lock : 1;
2357 	} bits;
2358 
2359 	/**
2360 	 * Union for HW Lock flags.
2361 	 */
2362 	uint8_t u8All;
2363 };
2364 
2365 /**
2366  * Instances of HW to be locked.
2367  *
2368  * Note: If updating with more HW components, fields
2369  * in dmub_inbox0_cmd_lock_hw must be updated to match.
2370  */
2371 struct dmub_hw_lock_inst_flags {
2372 	/**
2373 	 * OTG HW instance for OTG master update lock.
2374 	 */
2375 	uint8_t otg_inst;
2376 	/**
2377 	 * OPP instance for cursor lock.
2378 	 */
2379 	uint8_t opp_inst;
2380 	/**
2381 	 * OTG HW instance for global update lock.
2382 	 * TODO: Remove, and re-use otg_inst.
2383 	 */
2384 	uint8_t dig_inst;
2385 	/**
2386 	 * Explicit pad to 4 byte boundary.
2387 	 */
2388 	uint8_t pad;
2389 };
2390 
2391 /**
2392  * Clients that can acquire the HW Lock Manager.
2393  *
2394  * Note: If updating with more clients, fields in
2395  * dmub_inbox0_cmd_lock_hw must be updated to match.
2396  */
2397 enum hw_lock_client {
2398 	/**
2399 	 * Driver is the client of HW Lock Manager.
2400 	 */
2401 	HW_LOCK_CLIENT_DRIVER = 0,
2402 	/**
2403 	 * PSR SU is the client of HW Lock Manager.
2404 	 */
2405 	HW_LOCK_CLIENT_PSR_SU		= 1,
2406 	/**
2407 	 * Invalid client.
2408 	 */
2409 	HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
2410 };
2411 
2412 /**
2413  * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
2414  */
2415 struct dmub_cmd_lock_hw_data {
2416 	/**
2417 	 * Specifies the client accessing HW Lock Manager.
2418 	 */
2419 	enum hw_lock_client client;
2420 	/**
2421 	 * HW instances to be locked.
2422 	 */
2423 	struct dmub_hw_lock_inst_flags inst_flags;
2424 	/**
2425 	 * Which components to be locked.
2426 	 */
2427 	union dmub_hw_lock_flags hw_locks;
2428 	/**
2429 	 * Specifies lock/unlock.
2430 	 */
2431 	uint8_t lock;
2432 	/**
2433 	 * HW can be unlocked separately from releasing the HW Lock Mgr.
2434 	 * This flag is set if the client wishes to release the object.
2435 	 */
2436 	uint8_t should_release;
2437 	/**
2438 	 * Explicit padding to 4 byte boundary.
2439 	 */
2440 	uint8_t pad;
2441 };
2442 
2443 /**
2444  * Definition of a DMUB_CMD__HW_LOCK command.
2445  * Command is used by driver and FW.
2446  */
2447 struct dmub_rb_cmd_lock_hw {
2448 	/**
2449 	 * Command header.
2450 	 */
2451 	struct dmub_cmd_header header;
2452 	/**
2453 	 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
2454 	 */
2455 	struct dmub_cmd_lock_hw_data lock_hw_data;
2456 };
2457 
2458 /**
2459  * ABM command sub-types.
2460  */
2461 enum dmub_cmd_abm_type {
2462 	/**
2463 	 * Initialize parameters for ABM algorithm.
2464 	 * Data is passed through an indirect buffer.
2465 	 */
2466 	DMUB_CMD__ABM_INIT_CONFIG	= 0,
2467 	/**
2468 	 * Set OTG and panel HW instance.
2469 	 */
2470 	DMUB_CMD__ABM_SET_PIPE		= 1,
2471 	/**
2472 	 * Set user requested backklight level.
2473 	 */
2474 	DMUB_CMD__ABM_SET_BACKLIGHT	= 2,
2475 	/**
2476 	 * Set ABM operating/aggression level.
2477 	 */
2478 	DMUB_CMD__ABM_SET_LEVEL		= 3,
2479 	/**
2480 	 * Set ambient light level.
2481 	 */
2482 	DMUB_CMD__ABM_SET_AMBIENT_LEVEL	= 4,
2483 	/**
2484 	 * Enable/disable fractional duty cycle for backlight PWM.
2485 	 */
2486 	DMUB_CMD__ABM_SET_PWM_FRAC	= 5,
2487 
2488 	/**
2489 	 * unregister vertical interrupt after steady state is reached
2490 	 */
2491 	DMUB_CMD__ABM_PAUSE	= 6,
2492 };
2493 
2494 /**
2495  * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
2496  * Requirements:
2497  *  - Padded explicitly to 32-bit boundary.
2498  *  - Must ensure this structure matches the one on driver-side,
2499  *    otherwise it won't be aligned.
2500  */
2501 struct abm_config_table {
2502 	/**
2503 	 * Gamma curve thresholds, used for crgb conversion.
2504 	 */
2505 	uint16_t crgb_thresh[NUM_POWER_FN_SEGS];                 // 0B
2506 	/**
2507 	 * Gamma curve offsets, used for crgb conversion.
2508 	 */
2509 	uint16_t crgb_offset[NUM_POWER_FN_SEGS];                 // 16B
2510 	/**
2511 	 * Gamma curve slopes, used for crgb conversion.
2512 	 */
2513 	uint16_t crgb_slope[NUM_POWER_FN_SEGS];                  // 32B
2514 	/**
2515 	 * Custom backlight curve thresholds.
2516 	 */
2517 	uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS];        // 48B
2518 	/**
2519 	 * Custom backlight curve offsets.
2520 	 */
2521 	uint16_t backlight_offsets[NUM_BL_CURVE_SEGS];           // 78B
2522 	/**
2523 	 * Ambient light thresholds.
2524 	 */
2525 	uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL];         // 112B
2526 	/**
2527 	 * Minimum programmable backlight.
2528 	 */
2529 	uint16_t min_abm_backlight;                              // 122B
2530 	/**
2531 	 * Minimum reduction values.
2532 	 */
2533 	uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];   // 124B
2534 	/**
2535 	 * Maximum reduction values.
2536 	 */
2537 	uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];   // 144B
2538 	/**
2539 	 * Bright positive gain.
2540 	 */
2541 	uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
2542 	/**
2543 	 * Dark negative gain.
2544 	 */
2545 	uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];   // 184B
2546 	/**
2547 	 * Hybrid factor.
2548 	 */
2549 	uint8_t hybrid_factor[NUM_AGGR_LEVEL];                   // 204B
2550 	/**
2551 	 * Contrast factor.
2552 	 */
2553 	uint8_t contrast_factor[NUM_AGGR_LEVEL];                 // 208B
2554 	/**
2555 	 * Deviation gain.
2556 	 */
2557 	uint8_t deviation_gain[NUM_AGGR_LEVEL];                  // 212B
2558 	/**
2559 	 * Minimum knee.
2560 	 */
2561 	uint8_t min_knee[NUM_AGGR_LEVEL];                        // 216B
2562 	/**
2563 	 * Maximum knee.
2564 	 */
2565 	uint8_t max_knee[NUM_AGGR_LEVEL];                        // 220B
2566 	/**
2567 	 * Unused.
2568 	 */
2569 	uint8_t iir_curve[NUM_AMBI_LEVEL];                       // 224B
2570 	/**
2571 	 * Explicit padding to 4 byte boundary.
2572 	 */
2573 	uint8_t pad3[3];                                         // 229B
2574 	/**
2575 	 * Backlight ramp reduction.
2576 	 */
2577 	uint16_t blRampReduction[NUM_AGGR_LEVEL];                // 232B
2578 	/**
2579 	 * Backlight ramp start.
2580 	 */
2581 	uint16_t blRampStart[NUM_AGGR_LEVEL];                    // 240B
2582 };
2583 
2584 /**
2585  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
2586  */
2587 struct dmub_cmd_abm_set_pipe_data {
2588 	/**
2589 	 * OTG HW instance.
2590 	 */
2591 	uint8_t otg_inst;
2592 
2593 	/**
2594 	 * Panel Control HW instance.
2595 	 */
2596 	uint8_t panel_inst;
2597 
2598 	/**
2599 	 * Controls how ABM will interpret a set pipe or set level command.
2600 	 */
2601 	uint8_t set_pipe_option;
2602 
2603 	/**
2604 	 * Unused.
2605 	 * TODO: Remove.
2606 	 */
2607 	uint8_t ramping_boundary;
2608 };
2609 
2610 /**
2611  * Definition of a DMUB_CMD__ABM_SET_PIPE command.
2612  */
2613 struct dmub_rb_cmd_abm_set_pipe {
2614 	/**
2615 	 * Command header.
2616 	 */
2617 	struct dmub_cmd_header header;
2618 
2619 	/**
2620 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
2621 	 */
2622 	struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
2623 };
2624 
2625 /**
2626  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
2627  */
2628 struct dmub_cmd_abm_set_backlight_data {
2629 	/**
2630 	 * Number of frames to ramp to backlight user level.
2631 	 */
2632 	uint32_t frame_ramp;
2633 
2634 	/**
2635 	 * Requested backlight level from user.
2636 	 */
2637 	uint32_t backlight_user_level;
2638 
2639 	/**
2640 	 * ABM control version.
2641 	 */
2642 	uint8_t version;
2643 
2644 	/**
2645 	 * Panel Control HW instance mask.
2646 	 * Bit 0 is Panel Control HW instance 0.
2647 	 * Bit 1 is Panel Control HW instance 1.
2648 	 */
2649 	uint8_t panel_mask;
2650 
2651 	/**
2652 	 * Explicit padding to 4 byte boundary.
2653 	 */
2654 	uint8_t pad[2];
2655 };
2656 
2657 /**
2658  * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
2659  */
2660 struct dmub_rb_cmd_abm_set_backlight {
2661 	/**
2662 	 * Command header.
2663 	 */
2664 	struct dmub_cmd_header header;
2665 
2666 	/**
2667 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
2668 	 */
2669 	struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
2670 };
2671 
2672 /**
2673  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
2674  */
2675 struct dmub_cmd_abm_set_level_data {
2676 	/**
2677 	 * Set current ABM operating/aggression level.
2678 	 */
2679 	uint32_t level;
2680 
2681 	/**
2682 	 * ABM control version.
2683 	 */
2684 	uint8_t version;
2685 
2686 	/**
2687 	 * Panel Control HW instance mask.
2688 	 * Bit 0 is Panel Control HW instance 0.
2689 	 * Bit 1 is Panel Control HW instance 1.
2690 	 */
2691 	uint8_t panel_mask;
2692 
2693 	/**
2694 	 * Explicit padding to 4 byte boundary.
2695 	 */
2696 	uint8_t pad[2];
2697 };
2698 
2699 /**
2700  * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
2701  */
2702 struct dmub_rb_cmd_abm_set_level {
2703 	/**
2704 	 * Command header.
2705 	 */
2706 	struct dmub_cmd_header header;
2707 
2708 	/**
2709 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
2710 	 */
2711 	struct dmub_cmd_abm_set_level_data abm_set_level_data;
2712 };
2713 
2714 /**
2715  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
2716  */
2717 struct dmub_cmd_abm_set_ambient_level_data {
2718 	/**
2719 	 * Ambient light sensor reading from OS.
2720 	 */
2721 	uint32_t ambient_lux;
2722 
2723 	/**
2724 	 * ABM control version.
2725 	 */
2726 	uint8_t version;
2727 
2728 	/**
2729 	 * Panel Control HW instance mask.
2730 	 * Bit 0 is Panel Control HW instance 0.
2731 	 * Bit 1 is Panel Control HW instance 1.
2732 	 */
2733 	uint8_t panel_mask;
2734 
2735 	/**
2736 	 * Explicit padding to 4 byte boundary.
2737 	 */
2738 	uint8_t pad[2];
2739 };
2740 
2741 /**
2742  * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
2743  */
2744 struct dmub_rb_cmd_abm_set_ambient_level {
2745 	/**
2746 	 * Command header.
2747 	 */
2748 	struct dmub_cmd_header header;
2749 
2750 	/**
2751 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
2752 	 */
2753 	struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
2754 };
2755 
2756 /**
2757  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
2758  */
2759 struct dmub_cmd_abm_set_pwm_frac_data {
2760 	/**
2761 	 * Enable/disable fractional duty cycle for backlight PWM.
2762 	 * TODO: Convert to uint8_t.
2763 	 */
2764 	uint32_t fractional_pwm;
2765 
2766 	/**
2767 	 * ABM control version.
2768 	 */
2769 	uint8_t version;
2770 
2771 	/**
2772 	 * Panel Control HW instance mask.
2773 	 * Bit 0 is Panel Control HW instance 0.
2774 	 * Bit 1 is Panel Control HW instance 1.
2775 	 */
2776 	uint8_t panel_mask;
2777 
2778 	/**
2779 	 * Explicit padding to 4 byte boundary.
2780 	 */
2781 	uint8_t pad[2];
2782 };
2783 
2784 /**
2785  * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
2786  */
2787 struct dmub_rb_cmd_abm_set_pwm_frac {
2788 	/**
2789 	 * Command header.
2790 	 */
2791 	struct dmub_cmd_header header;
2792 
2793 	/**
2794 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
2795 	 */
2796 	struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
2797 };
2798 
2799 /**
2800  * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
2801  */
2802 struct dmub_cmd_abm_init_config_data {
2803 	/**
2804 	 * Location of indirect buffer used to pass init data to ABM.
2805 	 */
2806 	union dmub_addr src;
2807 
2808 	/**
2809 	 * Indirect buffer length.
2810 	 */
2811 	uint16_t bytes;
2812 
2813 
2814 	/**
2815 	 * ABM control version.
2816 	 */
2817 	uint8_t version;
2818 
2819 	/**
2820 	 * Panel Control HW instance mask.
2821 	 * Bit 0 is Panel Control HW instance 0.
2822 	 * Bit 1 is Panel Control HW instance 1.
2823 	 */
2824 	uint8_t panel_mask;
2825 
2826 	/**
2827 	 * Explicit padding to 4 byte boundary.
2828 	 */
2829 	uint8_t pad[2];
2830 };
2831 
2832 /**
2833  * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
2834  */
2835 struct dmub_rb_cmd_abm_init_config {
2836 	/**
2837 	 * Command header.
2838 	 */
2839 	struct dmub_cmd_header header;
2840 
2841 	/**
2842 	 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
2843 	 */
2844 	struct dmub_cmd_abm_init_config_data abm_init_config_data;
2845 };
2846 
2847 /**
2848  * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
2849  */
2850 
2851 struct dmub_cmd_abm_pause_data {
2852 
2853 	/**
2854 	 * Panel Control HW instance mask.
2855 	 * Bit 0 is Panel Control HW instance 0.
2856 	 * Bit 1 is Panel Control HW instance 1.
2857 	 */
2858 	uint8_t panel_mask;
2859 
2860 	/**
2861 	 * OTG hw instance
2862 	 */
2863 	uint8_t otg_inst;
2864 
2865 	/**
2866 	 * Enable or disable ABM pause
2867 	 */
2868 	uint8_t enable;
2869 
2870 	/**
2871 	 * Explicit padding to 4 byte boundary.
2872 	 */
2873 	uint8_t pad[1];
2874 };
2875 
2876 /**
2877  * Definition of a DMUB_CMD__ABM_PAUSE command.
2878  */
2879 struct dmub_rb_cmd_abm_pause {
2880 	/**
2881 	 * Command header.
2882 	 */
2883 	struct dmub_cmd_header header;
2884 
2885 	/**
2886 	 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
2887 	 */
2888 	struct dmub_cmd_abm_pause_data abm_pause_data;
2889 };
2890 
2891 /**
2892  * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
2893  */
2894 struct dmub_cmd_query_feature_caps_data {
2895 	/**
2896 	 * DMUB feature capabilities.
2897 	 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
2898 	 */
2899 	struct dmub_feature_caps feature_caps;
2900 };
2901 
2902 /**
2903  * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
2904  */
2905 struct dmub_rb_cmd_query_feature_caps {
2906 	/**
2907 	 * Command header.
2908 	 */
2909 	struct dmub_cmd_header header;
2910 	/**
2911 	 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
2912 	 */
2913 	struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
2914 };
2915 
2916 /**
2917  * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
2918  */
2919 struct dmub_cmd_visual_confirm_color_data {
2920 	/**
2921 	 * DMUB feature capabilities.
2922 	 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
2923 	 */
2924 struct dmub_visual_confirm_color visual_confirm_color;
2925 };
2926 
2927 /**
2928  * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
2929  */
2930 struct dmub_rb_cmd_get_visual_confirm_color {
2931  /**
2932 	 * Command header.
2933 	 */
2934 	struct dmub_cmd_header header;
2935 	/**
2936 	 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
2937 	 */
2938 	struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
2939 };
2940 
2941 struct dmub_optc_state {
2942 	uint32_t v_total_max;
2943 	uint32_t v_total_min;
2944 	uint32_t tg_inst;
2945 };
2946 
2947 struct dmub_rb_cmd_drr_update {
2948 		struct dmub_cmd_header header;
2949 		struct dmub_optc_state dmub_optc_state_req;
2950 };
2951 
2952 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
2953 	uint32_t pix_clk_100hz;
2954 	uint8_t max_ramp_step;
2955 	uint8_t pipes;
2956 	uint8_t min_refresh_in_hz;
2957 	uint8_t padding[1];
2958 };
2959 
2960 struct dmub_cmd_fw_assisted_mclk_switch_config {
2961 	uint8_t fams_enabled;
2962 	uint8_t visual_confirm_enabled;
2963 	uint8_t padding[2];
2964 	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS];
2965 };
2966 
2967 struct dmub_rb_cmd_fw_assisted_mclk_switch {
2968 	struct dmub_cmd_header header;
2969 	struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
2970 };
2971 
2972 /**
2973  * enum dmub_cmd_panel_cntl_type - Panel control command.
2974  */
2975 enum dmub_cmd_panel_cntl_type {
2976 	/**
2977 	 * Initializes embedded panel hardware blocks.
2978 	 */
2979 	DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
2980 	/**
2981 	 * Queries backlight info for the embedded panel.
2982 	 */
2983 	DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
2984 };
2985 
2986 /**
2987  * struct dmub_cmd_panel_cntl_data - Panel control data.
2988  */
2989 struct dmub_cmd_panel_cntl_data {
2990 	uint32_t inst; /**< panel instance */
2991 	uint32_t current_backlight; /* in/out */
2992 	uint32_t bl_pwm_cntl; /* in/out */
2993 	uint32_t bl_pwm_period_cntl; /* in/out */
2994 	uint32_t bl_pwm_ref_div1; /* in/out */
2995 	uint8_t is_backlight_on : 1; /* in/out */
2996 	uint8_t is_powered_on : 1; /* in/out */
2997 	uint8_t padding[3];
2998 	uint32_t bl_pwm_ref_div2; /* in/out */
2999 	uint8_t reserved[4];
3000 };
3001 
3002 /**
3003  * struct dmub_rb_cmd_panel_cntl - Panel control command.
3004  */
3005 struct dmub_rb_cmd_panel_cntl {
3006 	struct dmub_cmd_header header; /**< header */
3007 	struct dmub_cmd_panel_cntl_data data; /**< payload */
3008 };
3009 
3010 /**
3011  * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3012  */
3013 struct dmub_cmd_lvtma_control_data {
3014 	uint8_t uc_pwr_action; /**< LVTMA_ACTION */
3015 	uint8_t reserved_0[3]; /**< For future use */
3016 	uint8_t panel_inst; /**< LVTMA control instance */
3017 	uint8_t reserved_1[3]; /**< For future use */
3018 };
3019 
3020 /**
3021  * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3022  */
3023 struct dmub_rb_cmd_lvtma_control {
3024 	/**
3025 	 * Command header.
3026 	 */
3027 	struct dmub_cmd_header header;
3028 	/**
3029 	 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3030 	 */
3031 	struct dmub_cmd_lvtma_control_data data;
3032 };
3033 
3034 /**
3035  * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
3036  */
3037 struct dmub_rb_cmd_transmitter_query_dp_alt_data {
3038 	uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
3039 	uint8_t is_usb; /**< is phy is usb */
3040 	uint8_t is_dp_alt_disable; /**< is dp alt disable */
3041 	uint8_t is_dp4; /**< is dp in 4 lane */
3042 };
3043 
3044 /**
3045  * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
3046  */
3047 struct dmub_rb_cmd_transmitter_query_dp_alt {
3048 	struct dmub_cmd_header header; /**< header */
3049 	struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */
3050 };
3051 
3052 /**
3053  * Maximum number of bytes a chunk sent to DMUB for parsing
3054  */
3055 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
3056 
3057 /**
3058  *  Represent a chunk of CEA blocks sent to DMUB for parsing
3059  */
3060 struct dmub_cmd_send_edid_cea {
3061 	uint16_t offset;	/**< offset into the CEA block */
3062 	uint8_t length;	/**< number of bytes in payload to copy as part of CEA block */
3063 	uint16_t cea_total_length;  /**< total length of the CEA block */
3064 	uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
3065 	uint8_t pad[3]; /**< padding and for future expansion */
3066 };
3067 
3068 /**
3069  * Result of VSDB parsing from CEA block
3070  */
3071 struct dmub_cmd_edid_cea_amd_vsdb {
3072 	uint8_t vsdb_found;		/**< 1 if parsing has found valid AMD VSDB */
3073 	uint8_t freesync_supported;	/**< 1 if Freesync is supported */
3074 	uint16_t amd_vsdb_version;	/**< AMD VSDB version */
3075 	uint16_t min_frame_rate;	/**< Maximum frame rate */
3076 	uint16_t max_frame_rate;	/**< Minimum frame rate */
3077 };
3078 
3079 /**
3080  * Result of sending a CEA chunk
3081  */
3082 struct dmub_cmd_edid_cea_ack {
3083 	uint16_t offset;	/**< offset of the chunk into the CEA block */
3084 	uint8_t success;	/**< 1 if this sending of chunk succeeded */
3085 	uint8_t pad;		/**< padding and for future expansion */
3086 };
3087 
3088 /**
3089  * Specify whether the result is an ACK/NACK or the parsing has finished
3090  */
3091 enum dmub_cmd_edid_cea_reply_type {
3092 	DMUB_CMD__EDID_CEA_AMD_VSDB	= 1, /**< VSDB parsing has finished */
3093 	DMUB_CMD__EDID_CEA_ACK		= 2, /**< acknowledges the CEA sending is OK or failing */
3094 };
3095 
3096 /**
3097  * Definition of a DMUB_CMD__EDID_CEA command.
3098  */
3099 struct dmub_rb_cmd_edid_cea {
3100 	struct dmub_cmd_header header;	/**< Command header */
3101 	union dmub_cmd_edid_cea_data {
3102 		struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
3103 		struct dmub_cmd_edid_cea_output { /**< output with results */
3104 			uint8_t type;	/**< dmub_cmd_edid_cea_reply_type */
3105 			union {
3106 				struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
3107 				struct dmub_cmd_edid_cea_ack ack;
3108 			};
3109 		} output;	/**< output to retrieve ACK/NACK or VSDB parsing results */
3110 	} data;	/**< Command data */
3111 
3112 };
3113 
3114 /**
3115  * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command.
3116  */
3117 struct dmub_cmd_cable_id_input {
3118 	uint8_t phy_inst;  /**< phy inst for cable id data */
3119 };
3120 
3121 /**
3122  * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command.
3123  */
3124 struct dmub_cmd_cable_id_output {
3125 	uint8_t UHBR10_20_CAPABILITY	:2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */
3126 	uint8_t UHBR13_5_CAPABILITY	:1; /**< b'1 for UHBR13.5 support */
3127 	uint8_t CABLE_TYPE		:3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */
3128 	uint8_t RESERVED		:2; /**< reserved means not defined */
3129 };
3130 
3131 /**
3132  * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command
3133  */
3134 struct dmub_rb_cmd_get_usbc_cable_id {
3135 	struct dmub_cmd_header header; /**< Command header */
3136 	/**
3137 	 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command.
3138 	 */
3139 	union dmub_cmd_cable_id_data {
3140 		struct dmub_cmd_cable_id_input input; /**< Input */
3141 		struct dmub_cmd_cable_id_output output; /**< Output */
3142 		uint8_t output_raw; /**< Raw data output */
3143 	} data;
3144 };
3145 
3146 /**
3147  * union dmub_rb_cmd - DMUB inbox command.
3148  */
3149 union dmub_rb_cmd {
3150 	/**
3151 	 * Elements shared with all commands.
3152 	 */
3153 	struct dmub_rb_cmd_common cmd_common;
3154 	/**
3155 	 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
3156 	 */
3157 	struct dmub_rb_cmd_read_modify_write read_modify_write;
3158 	/**
3159 	 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
3160 	 */
3161 	struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
3162 	/**
3163 	 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
3164 	 */
3165 	struct dmub_rb_cmd_burst_write burst_write;
3166 	/**
3167 	 * Definition of a DMUB_CMD__REG_REG_WAIT command.
3168 	 */
3169 	struct dmub_rb_cmd_reg_wait reg_wait;
3170 	/**
3171 	 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
3172 	 */
3173 	struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
3174 	/**
3175 	 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
3176 	 */
3177 	struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
3178 	/**
3179 	 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
3180 	 */
3181 	struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
3182 	/**
3183 	 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
3184 	 */
3185 	struct dmub_rb_cmd_dpphy_init dpphy_init;
3186 	/**
3187 	 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
3188 	 */
3189 	struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
3190 	/**
3191 	 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
3192 	 */
3193 	struct dmub_rb_cmd_psr_set_version psr_set_version;
3194 	/**
3195 	 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
3196 	 */
3197 	struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
3198 	/**
3199 	 * Definition of a DMUB_CMD__PSR_ENABLE command.
3200 	 */
3201 	struct dmub_rb_cmd_psr_enable psr_enable;
3202 	/**
3203 	 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
3204 	 */
3205 	struct dmub_rb_cmd_psr_set_level psr_set_level;
3206 	/**
3207 	 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
3208 	 */
3209 	struct dmub_rb_cmd_psr_force_static psr_force_static;
3210 	/**
3211 	 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
3212 	 */
3213 	struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;
3214 	/**
3215 	 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
3216 	 */
3217 	struct dmub_rb_cmd_update_cursor_info update_cursor_info;
3218 	/**
3219 	 * Definition of a DMUB_CMD__HW_LOCK command.
3220 	 * Command is used by driver and FW.
3221 	 */
3222 	struct dmub_rb_cmd_lock_hw lock_hw;
3223 	/**
3224 	 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
3225 	 */
3226 	struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;
3227 	/**
3228 	 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3229 	 */
3230 	struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt;
3231 	/**
3232 	 * Definition of a DMUB_CMD__PLAT_54186_WA command.
3233 	 */
3234 	struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
3235 	/**
3236 	 * Definition of a DMUB_CMD__MALL command.
3237 	 */
3238 	struct dmub_rb_cmd_mall mall;
3239 	/**
3240 	 * Definition of a DMUB_CMD__CAB command.
3241 	 */
3242 	struct dmub_rb_cmd_cab_for_ss cab;
3243 
3244 	struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2;
3245 
3246 	/**
3247 	 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
3248 	 */
3249 	struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
3250 
3251 	/**
3252 	 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
3253 	 */
3254 	struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
3255 
3256 	/**
3257 	 * Definition of DMUB_CMD__PANEL_CNTL commands.
3258 	 */
3259 	struct dmub_rb_cmd_panel_cntl panel_cntl;
3260 	/**
3261 	 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
3262 	 */
3263 	struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
3264 
3265 	/**
3266 	 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
3267 	 */
3268 	struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
3269 
3270 	/**
3271 	 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
3272 	 */
3273 	struct dmub_rb_cmd_abm_set_level abm_set_level;
3274 
3275 	/**
3276 	 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
3277 	 */
3278 	struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
3279 
3280 	/**
3281 	 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
3282 	 */
3283 	struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
3284 
3285 	/**
3286 	 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
3287 	 */
3288 	struct dmub_rb_cmd_abm_init_config abm_init_config;
3289 
3290 	/**
3291 	 * Definition of a DMUB_CMD__ABM_PAUSE command.
3292 	 */
3293 	struct dmub_rb_cmd_abm_pause abm_pause;
3294 
3295 	/**
3296 	 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
3297 	 */
3298 	struct dmub_rb_cmd_dp_aux_access dp_aux_access;
3299 
3300 	/**
3301 	 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
3302 	 */
3303 	struct dmub_rb_cmd_outbox1_enable outbox1_enable;
3304 
3305 	/**
3306 	 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
3307 	 */
3308 	struct dmub_rb_cmd_query_feature_caps query_feature_caps;
3309 
3310 	/**
3311 	 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3312 	 */
3313 	struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;
3314 	struct dmub_rb_cmd_drr_update drr_update;
3315 	struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;
3316 
3317 	/**
3318 	 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3319 	 */
3320 	struct dmub_rb_cmd_lvtma_control lvtma_control;
3321 	/**
3322 	 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
3323 	 */
3324 	struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt;
3325 	/**
3326 	 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.
3327 	 */
3328 	struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control;
3329 	/**
3330 	 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
3331 	 */
3332 	struct dmub_rb_cmd_set_config_access set_config_access;
3333 	/**
3334 	 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
3335 	 */
3336 	struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots;
3337 	/**
3338 	 * Definition of a DMUB_CMD__EDID_CEA command.
3339 	 */
3340 	struct dmub_rb_cmd_edid_cea edid_cea;
3341 	/**
3342 	 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command.
3343 	 */
3344 	struct dmub_rb_cmd_get_usbc_cable_id cable_id;
3345 
3346 	/**
3347 	 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
3348 	 */
3349 	struct dmub_rb_cmd_query_hpd_state query_hpd;
3350 	/**
3351 	 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command.
3352 	 */
3353 	struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable;
3354 };
3355 
3356 /**
3357  * union dmub_rb_out_cmd - Outbox command
3358  */
3359 union dmub_rb_out_cmd {
3360 	/**
3361 	 * Parameters common to every command.
3362 	 */
3363 	struct dmub_rb_cmd_common cmd_common;
3364 	/**
3365 	 * AUX reply command.
3366 	 */
3367 	struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
3368 	/**
3369 	 * HPD notify command.
3370 	 */
3371 	struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
3372 	/**
3373 	 * SET_CONFIG reply command.
3374 	 */
3375 	struct dmub_rb_cmd_dp_set_config_reply set_config_reply;
3376 };
3377 #pragma pack(pop)
3378 
3379 
3380 //==============================================================================
3381 //</DMUB_CMD>===================================================================
3382 //==============================================================================
3383 //< DMUB_RB>====================================================================
3384 //==============================================================================
3385 
3386 #if defined(__cplusplus)
3387 extern "C" {
3388 #endif
3389 
3390 /**
3391  * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
3392  */
3393 struct dmub_rb_init_params {
3394 	void *ctx; /**< Caller provided context pointer */
3395 	void *base_address; /**< CPU base address for ring's data */
3396 	uint32_t capacity; /**< Ringbuffer capacity in bytes */
3397 	uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
3398 	uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
3399 };
3400 
3401 /**
3402  * struct dmub_rb - Inbox or outbox DMUB ringbuffer
3403  */
3404 struct dmub_rb {
3405 	void *base_address; /**< CPU address for the ring's data */
3406 	uint32_t rptr; /**< Read pointer for consumer in bytes */
3407 	uint32_t wrpt; /**< Write pointer for producer in bytes */
3408 	uint32_t capacity; /**< Ringbuffer capacity in bytes */
3409 
3410 	void *ctx; /**< Caller provided context pointer */
3411 	void *dmub; /**< Pointer to the DMUB interface */
3412 };
3413 
3414 /**
3415  * @brief Checks if the ringbuffer is empty.
3416  *
3417  * @param rb DMUB Ringbuffer
3418  * @return true if empty
3419  * @return false otherwise
3420  */
dmub_rb_empty(struct dmub_rb * rb)3421 static inline bool dmub_rb_empty(struct dmub_rb *rb)
3422 {
3423 	return (rb->wrpt == rb->rptr);
3424 }
3425 
3426 /**
3427  * @brief Checks if the ringbuffer is full
3428  *
3429  * @param rb DMUB Ringbuffer
3430  * @return true if full
3431  * @return false otherwise
3432  */
dmub_rb_full(struct dmub_rb * rb)3433 static inline bool dmub_rb_full(struct dmub_rb *rb)
3434 {
3435 	uint32_t data_count;
3436 
3437 	if (rb->wrpt >= rb->rptr)
3438 		data_count = rb->wrpt - rb->rptr;
3439 	else
3440 		data_count = rb->capacity - (rb->rptr - rb->wrpt);
3441 
3442 	return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
3443 }
3444 
3445 /**
3446  * @brief Pushes a command into the ringbuffer
3447  *
3448  * @param rb DMUB ringbuffer
3449  * @param cmd The command to push
3450  * @return true if the ringbuffer was not full
3451  * @return false otherwise
3452  */
dmub_rb_push_front(struct dmub_rb * rb,const union dmub_rb_cmd * cmd)3453 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
3454 				      const union dmub_rb_cmd *cmd)
3455 {
3456 	uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt);
3457 	const uint64_t *src = (const uint64_t *)cmd;
3458 	uint8_t i;
3459 
3460 	if (dmub_rb_full(rb))
3461 		return false;
3462 
3463 	// copying data
3464 	for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
3465 		*dst++ = *src++;
3466 
3467 	rb->wrpt += DMUB_RB_CMD_SIZE;
3468 
3469 	if (rb->wrpt >= rb->capacity)
3470 		rb->wrpt %= rb->capacity;
3471 
3472 	return true;
3473 }
3474 
3475 /**
3476  * @brief Pushes a command into the DMUB outbox ringbuffer
3477  *
3478  * @param rb DMUB outbox ringbuffer
3479  * @param cmd Outbox command
3480  * @return true if not full
3481  * @return false otherwise
3482  */
dmub_rb_out_push_front(struct dmub_rb * rb,const union dmub_rb_out_cmd * cmd)3483 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
3484 				      const union dmub_rb_out_cmd *cmd)
3485 {
3486 	uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
3487 	const uint8_t *src = (const uint8_t *)cmd;
3488 
3489 	if (dmub_rb_full(rb))
3490 		return false;
3491 
3492 	dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
3493 
3494 	rb->wrpt += DMUB_RB_CMD_SIZE;
3495 
3496 	if (rb->wrpt >= rb->capacity)
3497 		rb->wrpt %= rb->capacity;
3498 
3499 	return true;
3500 }
3501 
3502 /**
3503  * @brief Returns the next unprocessed command in the ringbuffer.
3504  *
3505  * @param rb DMUB ringbuffer
3506  * @param cmd The command to return
3507  * @return true if not empty
3508  * @return false otherwise
3509  */
dmub_rb_front(struct dmub_rb * rb,union dmub_rb_cmd ** cmd)3510 static inline bool dmub_rb_front(struct dmub_rb *rb,
3511 				 union dmub_rb_cmd  **cmd)
3512 {
3513 	uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
3514 
3515 	if (dmub_rb_empty(rb))
3516 		return false;
3517 
3518 	*cmd = (union dmub_rb_cmd *)rb_cmd;
3519 
3520 	return true;
3521 }
3522 
3523 /**
3524  * @brief Determines the next ringbuffer offset.
3525  *
3526  * @param rb DMUB inbox ringbuffer
3527  * @param num_cmds Number of commands
3528  * @param next_rptr The next offset in the ringbuffer
3529  */
dmub_rb_get_rptr_with_offset(struct dmub_rb * rb,uint32_t num_cmds,uint32_t * next_rptr)3530 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
3531 				  uint32_t num_cmds,
3532 				  uint32_t *next_rptr)
3533 {
3534 	*next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
3535 
3536 	if (*next_rptr >= rb->capacity)
3537 		*next_rptr %= rb->capacity;
3538 }
3539 
3540 /**
3541  * @brief Returns a pointer to a command in the inbox.
3542  *
3543  * @param rb DMUB inbox ringbuffer
3544  * @param cmd The inbox command to return
3545  * @param rptr The ringbuffer offset
3546  * @return true if not empty
3547  * @return false otherwise
3548  */
dmub_rb_peek_offset(struct dmub_rb * rb,union dmub_rb_cmd ** cmd,uint32_t rptr)3549 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
3550 				 union dmub_rb_cmd  **cmd,
3551 				 uint32_t rptr)
3552 {
3553 	uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
3554 
3555 	if (dmub_rb_empty(rb))
3556 		return false;
3557 
3558 	*cmd = (union dmub_rb_cmd *)rb_cmd;
3559 
3560 	return true;
3561 }
3562 
3563 /**
3564  * @brief Returns the next unprocessed command in the outbox.
3565  *
3566  * @param rb DMUB outbox ringbuffer
3567  * @param cmd The outbox command to return
3568  * @return true if not empty
3569  * @return false otherwise
3570  */
dmub_rb_out_front(struct dmub_rb * rb,union dmub_rb_out_cmd * cmd)3571 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
3572 				 union dmub_rb_out_cmd *cmd)
3573 {
3574 	const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr);
3575 	uint64_t *dst = (uint64_t *)cmd;
3576 	uint8_t i;
3577 
3578 	if (dmub_rb_empty(rb))
3579 		return false;
3580 
3581 	// copying data
3582 	for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
3583 		*dst++ = *src++;
3584 
3585 	return true;
3586 }
3587 
3588 /**
3589  * @brief Removes the front entry in the ringbuffer.
3590  *
3591  * @param rb DMUB ringbuffer
3592  * @return true if the command was removed
3593  * @return false if there were no commands
3594  */
dmub_rb_pop_front(struct dmub_rb * rb)3595 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
3596 {
3597 	if (dmub_rb_empty(rb))
3598 		return false;
3599 
3600 	rb->rptr += DMUB_RB_CMD_SIZE;
3601 
3602 	if (rb->rptr >= rb->capacity)
3603 		rb->rptr %= rb->capacity;
3604 
3605 	return true;
3606 }
3607 
3608 /**
3609  * @brief Flushes commands in the ringbuffer to framebuffer memory.
3610  *
3611  * Avoids a race condition where DMCUB accesses memory while
3612  * there are still writes in flight to framebuffer.
3613  *
3614  * @param rb DMUB ringbuffer
3615  */
dmub_rb_flush_pending(const struct dmub_rb * rb)3616 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
3617 {
3618 	uint32_t rptr = rb->rptr;
3619 	uint32_t wptr = rb->wrpt;
3620 
3621 	while (rptr != wptr) {
3622 		uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);
3623 		uint8_t i;
3624 
3625 		/* Don't remove this.
3626 		 * The contents need to actually be read from the ring buffer
3627 		 * for this function to be effective.
3628 		 */
3629 		for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
3630 			(void)READ_ONCE(*data++);
3631 
3632 		rptr += DMUB_RB_CMD_SIZE;
3633 		if (rptr >= rb->capacity)
3634 			rptr %= rb->capacity;
3635 	}
3636 }
3637 
3638 /**
3639  * @brief Initializes a DMCUB ringbuffer
3640  *
3641  * @param rb DMUB ringbuffer
3642  * @param init_params initial configuration for the ringbuffer
3643  */
dmub_rb_init(struct dmub_rb * rb,struct dmub_rb_init_params * init_params)3644 static inline void dmub_rb_init(struct dmub_rb *rb,
3645 				struct dmub_rb_init_params *init_params)
3646 {
3647 	rb->base_address = init_params->base_address;
3648 	rb->capacity = init_params->capacity;
3649 	rb->rptr = init_params->read_ptr;
3650 	rb->wrpt = init_params->write_ptr;
3651 }
3652 
3653 /**
3654  * @brief Copies output data from in/out commands into the given command.
3655  *
3656  * @param rb DMUB ringbuffer
3657  * @param cmd Command to copy data into
3658  */
dmub_rb_get_return_data(struct dmub_rb * rb,union dmub_rb_cmd * cmd)3659 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
3660 					   union dmub_rb_cmd *cmd)
3661 {
3662 	// Copy rb entry back into command
3663 	uint8_t *rd_ptr = (rb->rptr == 0) ?
3664 		(uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
3665 		(uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
3666 
3667 	dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
3668 }
3669 
3670 #if defined(__cplusplus)
3671 }
3672 #endif
3673 
3674 //==============================================================================
3675 //</DMUB_RB>====================================================================
3676 //==============================================================================
3677 
3678 #endif /* _DMUB_CMD_H_ */
3679