Searched refs:DKL_PLL_DIV1 (Results 1 – 2 of 2) sorted by relevance
3535 hw_state->mg_pll_div1 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port), 2); in dkl_pll_get_hw_state()3763 val = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port), 2); in dkl_pll_write()3767 intel_dkl_phy_write(dev_priv, DKL_PLL_DIV1(tc_port), 2, val); in dkl_pll_write()
7459 #define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ macro