Searched refs:DKL_PLL_DIV0 (Results 1 – 2 of 2) sorted by relevance
3529 hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port), 2); in dkl_pll_get_hw_state()3760 intel_dkl_phy_rmw(dev_priv, DKL_PLL_DIV0(tc_port), 2, val, in dkl_pll_write()
7450 #define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ macro