Searched refs:DISPLAY_MMIO_BASE (Results 1 – 3 of 3) sorted by relevance
11 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)12 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)16 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)17 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)21 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)22 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)27 #define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */50 #define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)72 #define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
11 #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
118 #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display.mmio_offset) macro166 DISPLAY_MMIO_BASE(dev_priv) + (reg))169 DISPLAY_MMIO_BASE(dev_priv) + (reg))172 DISPLAY_MMIO_BASE(dev_priv) + (reg))1471 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)1472 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)1473 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)1570 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)1571 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)1572 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)[all …]