Home
last modified time | relevance | path

Searched refs:DC__VOLTAGE_STATES (Results 1 – 13 of 13) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_mode_vba.h315 …double ActiveDRAMClockChangeLatencyMarginPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];// DML …
525 unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];
526 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];
588 double DCFCLKPerState[DC__VOLTAGE_STATES];
589 double DCFCLKState[DC__VOLTAGE_STATES][2];
590 double FabricClockPerState[DC__VOLTAGE_STATES];
591 double SOCCLKPerState[DC__VOLTAGE_STATES];
592 double PHYCLKPerState[DC__VOLTAGE_STATES];
593 double DTBCLKPerState[DC__VOLTAGE_STATES];
594 double MaxDppclk[DC__VOLTAGE_STATES];
[all …]
Ddc_features.h32 #define DC__VOLTAGE_STATES 20 macro
Ddisplay_mode_structs.h181 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn302/
Ddcn302_fpu.c200 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
201 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
202 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
203 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
205 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn302_fpu_update_bw_bounding_box()
282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
296 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
301 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn302_fpu_update_bw_bounding_box()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn303/
Ddcn303_fpu.c196 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
197 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
198 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
199 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
201 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn303_fpu_update_bw_bounding_box()
276 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
291 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
296 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn303_fpu_update_bw_bounding_box()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn321/
Ddcn321_fpu.c267 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in build_synthetic_soc_states()
558 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
559 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
560 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
561 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
563 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564}; in dcn321_update_bw_bounding_box_fpu()
627 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
641 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
646 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn321_update_bw_bounding_box_fpu()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_resource.c2103 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2104 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2105 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2106 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2108 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn30_update_bw_bounding_box()
2183 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2197 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2202 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn30_update_bw_bounding_box()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn32/
Ddcn32_fpu.c2112 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in build_synthetic_soc_states()
2399 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
2400 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
2401 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
2402 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
2406 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in dcn32_update_bw_bounding_box_fpu()
2475 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu()
2489 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu()
2494 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn32_update_bw_bounding_box_fpu()
Ddisplay_mode_vba_util_32.c2977 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2]; in dml32_UseMinimumDCFCLK()
2980 for (i = 0; i < DC__VOLTAGE_STATES; ++i) { in dml32_UseMinimumDCFCLK()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/
Ddc.h920 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_mode_vba_30.c6504 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2] = { { 0 } }; in UseMinimumDCFCLK()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_mode_vba_31.c6880 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn314/
Ddisplay_mode_vba_314.c6976 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];