Searched refs:Counter (Results 1 – 25 of 69) sorted by relevance
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19 typedef u_long Counter ; typedef29 Counter count ;195 Counter fddiMACFrame_Ct ;196 Counter fddiMACCopied_Ct ;197 Counter fddiMACTransmit_Ct ;198 Counter fddiMACToken_Ct ;199 Counter fddiMACError_Ct ;200 Counter fddiMACLost_Ct ;201 Counter fddiMACTvxExpired_Ct ;202 Counter fddiMACNotCopied_Ct ;[all …]
4 Generic Counter Interface10 Counter devices are prevalent among a diverse spectrum of industries.15 Generic Counter interface enables drivers to support and expose a common21 Counter devices can vary greatly in design, but regardless of whether25 the Generic Counter interface.45 When the Signal data is available for user access, the Generic Counter64 count data. The Generic Counter interface provides the following83 context of the Generic Counter interface, a counter consists of Counts94 Counter interface represents the count data as a natural number.97 for the count data. The Generic Counter interface provides the following[all …]
3 # Counter devices7 tristate "Counter support"9 This enables counter device support through the Generic Counter84 tristate "Microchip Timer Counter Capture driver"88 Select this option to enable the Microchip Timer Counter Block
164 - CTR (Counter) mode (NIST SP800-38A)181 - CTR (Counter) mode (NIST SP800-38A)212 - CTR (Counter) mode (NIST SP800-38A)244 - CTR (Counter) mode (NIST SP800-38A)261 - CTR (Counter) mode (NIST SP800-38A)275 CCM (Counter with Cipher Block Chaining-Message Authentication Code)
7 title: Arm SMMUv3 Performance Monitor Counter Group14 An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
12 The Counter Enable signal CNT_EN is used54 | Prescaler +-> | Counter | +-> | Master | TRGO(2)119 Counter is always ON.
50 whether Replay Protected Monotonic Counter support has been enabled.61 whether an Replay Protected Monotonic Counter supported SPI is installed
256 Size of the Counter events queue in number of struct265 the Counter. This should match the name of the device as it273 belonging to the Counter.280 belonging to the Counter.
1 OMAP Counter-32K bindings
1 * Cirrus Logic CLPS711X Timer Counter
7 title: Cadence TTC - Triple Timer Counter
7 title: NXP System Counter Module(sys_ctr)
4 Ingenic JZ47xx SoCs Timer/Counter Unit hardware7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
51 /* 64-bit Global Free Running Counter */
7 title: Atmel Timer Counter Block13 The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each
26 load_mem_type_cnt = collections.Counter()
72 by configuring BDF to "bdf". Counter only counts the bandwidth of message96 Counter counts when TLP length within the specified range. You can set the
30 - Counter value for the rpmb device will be read to stdout.
14 CR 0 (Recovery Counter) used for ptrace81 R (Recovery Counter trap) 0
83 Support the clocks of the Timer/Counter Unit (TCU) of the Ingenic
29 [Fixed Counter: Counts the number of instructions retired. Unit: cpu_atom]31 [Number of instructions retired. Fixed Counter - architectural event. Unit: cpu_core]
177 - CTR (Counter) mode (NIST SP800-38A)198 - CTR (Counter) mode (NIST SP800-38A)
27 # I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
29 14 counter Counter
38 Counter on/off registers.