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Searched refs:CSR (Results 1 – 25 of 44) sorted by relevance

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/linux-6.1.9/drivers/scsi/aacraid/
Daacraid.h1083 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1084 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1085 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) argument
1086 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) argument
1145 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) argument
1146 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) argument
1147 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) argument
1148 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR)) argument
1163 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) argument
1164 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) argument
[all …]
/linux-6.1.9/Documentation/devicetree/bindings/gnss/
Dsirfstar.yaml16 by CSR (Cambridge Silicon Radio) and in 2012 the CSR GPS business was
17 acquired by Samsung, while some products remained with CSR. In 2014 CSR
/linux-6.1.9/drivers/dma/
Dtxx9dmac.c296 channel64_readl(dc, CSR)); in txx9dmac_dump_regs()
308 channel32_readl(dc, CSR)); in txx9dmac_dump_regs()
339 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { in txx9dmac_dostart()
349 channel64_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
370 channel32_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
480 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
493 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
519 channel_writel(dc, CSR, errors); in txx9dmac_handle_error()
545 csr = channel64_readl(dc, CSR); in txx9dmac_scan_descriptors()
546 channel64_writel(dc, CSR, csr); in txx9dmac_scan_descriptors()
[all …]
Dtxx9dmac.h78 TXX9_DMA_REG32(CSR); /* Channel Status Register */
88 u32 CSR; member
/linux-6.1.9/Documentation/devicetree/bindings/clock/
Dxgene.txt36 - reg : shall be a list of address and length pairs describing the CSR
49 - csr-offset : Offset to the CSR reset register from the reset address base.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
55 - divider-offset : Offset to the divider CSR register from the divider base.
/linux-6.1.9/drivers/staging/qlge/
Dqlge_mpi.c9 tmp = qlge_read32(qdev, CSR); in qlge_unpause_mpi_risc()
13 qlge_write32(qdev, CSR, CSR_CMD_CLR_PAUSE); in qlge_unpause_mpi_risc()
23 qlge_write32(qdev, CSR, CSR_CMD_SET_PAUSE); in qlge_pause_mpi_risc()
25 tmp = qlge_read32(qdev, CSR); in qlge_pause_mpi_risc()
39 qlge_write32(qdev, CSR, CSR_CMD_SET_RST); in qlge_hard_reset_mpi_risc()
41 tmp = qlge_read32(qdev, CSR); in qlge_hard_reset_mpi_risc()
43 qlge_write32(qdev, CSR, CSR_CMD_CLR_RST); in qlge_hard_reset_mpi_risc()
170 if (qlge_read32(qdev, CSR) & CSR_HRI) in qlge_exec_mb_cmd()
189 qlge_write32(qdev, CSR, CSR_CMD_SET_H2R_INT); in qlge_exec_mb_cmd()
513 qlge_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT); in qlge_mpi_handler()
[all …]
/linux-6.1.9/Documentation/devicetree/bindings/mfd/
Dfsl,imx8qxp-csr.yaml14 Registers(CSR) module represents a set of miscellaneous registers of a
19 should consider all subnodes of the CSR module as separate child devices.
45 description: The possible child devices of the CSR module.
/linux-6.1.9/Documentation/devicetree/bindings/phy/
Dfsl,imx8qm-lvds-phy.yaml24 by Control and Status Registers(CSR) module in the SoC. The CSR
Dmixel,mipi-dsi-phy.yaml50 A phandle which points to Control and Status Registers(CSR) module.
/linux-6.1.9/Documentation/translations/zh_CN/loongarch/
Dirq-chip-model.rst151 - CPUINTC：即《龙芯架构参考手册卷一》第7.4节所描述的CSR.ECFG/CSR.ESTAT寄存器及其
/linux-6.1.9/Documentation/devicetree/bindings/display/bridge/
Dfsl,imx8qxp-pxl2dpi.yaml19 The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
20 The CSR module, as a system controller, contains the PXL2DPI's configuration
Dfsl,imx8qxp-ldb.yaml15 The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
16 The CSR module, as a system controller, contains the LDB's configuration
/linux-6.1.9/drivers/soc/litex/
DKconfig15 LiteX CSR access and provides common litex_[read|write]*
/linux-6.1.9/Documentation/devicetree/bindings/pci/
Daltera-pcie-msi.txt8 "csr": CSR registers
/linux-6.1.9/Documentation/devicetree/bindings/soc/litex/
Dlitex,soc-controller.yaml12 Its purpose is to verify LiteX CSR (Control&Status Register) access
/linux-6.1.9/Documentation/loongarch/
Dirq-chip-model.rst149 - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
/linux-6.1.9/arch/arm/mach-omap1/
Ddma.c59 [CSR] = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
219 l = dma_read(CSR, lch); in omap1_clear_dma()
Domap-dma.c87 p->dma_read(CSR, lch); in omap_disable_channel_irq()
325 p->dma_read(CSR, lch); in omap_enable_channel_irq()
711 csr = p->dma_read(CSR, ch); in omap1_dma_handle_ch()
/linux-6.1.9/arch/arm/mach-omap2/
Ddma.c57 [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
/linux-6.1.9/Documentation/devicetree/bindings/misc/
Didt_89hpesx.txt1 EEPROM / CSR SMBus-slave interface of IDT 89HPESx devices
/linux-6.1.9/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-sirf.txt1 CSR SiRFprimaII pinmux controller
/linux-6.1.9/Documentation/admin-guide/perf/
Dxgene-pmu.rst9 interrupt and status CSR region.
/linux-6.1.9/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.txt14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
/linux-6.1.9/Documentation/devicetree/bindings/soundwire/
Dqcom,sdw.txt168 Definition: Should specify the SoundWire audio CSR reset controller interface,
174 Definition: should be "swr_audio_cgcr" for SoundWire audio CSR reset
/linux-6.1.9/Documentation/arm/
Dixp4xx.rst39 require the use of Intel's proprietary CSR software:
140 the CSR or a WiFi card and a ramdisk that BOOTPs and then does

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