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Searched refs:CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK (Results 1 – 15 of 15) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2591 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v6_0_enable_mgcg()
2615 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { in gfx_v6_0_enable_mgcg()
2616 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v6_0_enable_mgcg()
Dgfx_v7_0.c3605 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v7_0_enable_mgcg()
3658 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { in gfx_v7_0_enable_mgcg()
3659 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v7_0_enable_mgcg()
Dgfx_v9_0.c4726 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v9_0_update_medium_grain_clock_gating()
4755 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { in gfx_v9_0_update_medium_grain_clock_gating()
4756 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v9_0_update_medium_grain_clock_gating()
5064 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) in gfx_v9_0_get_clockgating_state()
Dgfx_v8_0.c5500 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) in gfx_v8_0_get_clockgating_state()
5721 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { in gfx_v8_0_update_medium_grain_clock_gating()
5722 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v8_0_update_medium_grain_clock_gating()
Dgfx_v10_0.c7762 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v10_0_update_medium_grain_clock_gating()
7781 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { in gfx_v10_0_update_medium_grain_clock_gating()
7782 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v10_0_update_medium_grain_clock_gating()
8308 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) in gfx_v10_0_get_clockgating_state()
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h2598 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L macro
Dgfx_7_2_sh_mask.h1435 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 macro
Dgfx_8_0_sh_mask.h1879 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 macro
Dgfx_8_1_sh_mask.h2401 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h11213 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … macro
Dgc_9_1_sh_mask.h12694 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … macro
Dgc_9_2_1_sh_mask.h12492 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … macro
Dgc_9_4_2_sh_mask.h2601 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … macro
Dgc_10_1_0_sh_mask.h18180 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … macro
Dgc_10_3_0_sh_mask.h16531 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … macro