Home
last modified time | relevance | path

Searched refs:CP_HQD_PQ_CONTROL (Results 1 – 12 of 12) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dmes_v10_1.c770 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in mes_v10_1_mqd_init()
772 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in mes_v10_1_mqd_init()
775 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in mes_v10_1_mqd_init()
777 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); in mes_v10_1_mqd_init()
778 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); in mes_v10_1_mqd_init()
779 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in mes_v10_1_mqd_init()
780 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in mes_v10_1_mqd_init()
781 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); in mes_v10_1_mqd_init()
Dmes_v11_0.c821 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in mes_v11_0_mqd_init()
823 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in mes_v11_0_mqd_init()
825 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); in mes_v11_0_mqd_init()
826 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); in mes_v11_0_mqd_init()
827 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in mes_v11_0_mqd_init()
828 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in mes_v11_0_mqd_init()
829 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); in mes_v11_0_mqd_init()
Damdgpu_amdkfd_gfx_v10.c252 CP_HQD_PQ_CONTROL, QUEUE_SIZE); in kgd_hqd_load()
Damdgpu_amdkfd_gfx_v11.c224 CP_HQD_PQ_CONTROL, QUEUE_SIZE); in hqd_load_v11()
Damdgpu_amdkfd_gfx_v9.c266 CP_HQD_PQ_CONTROL, QUEUE_SIZE); in kgd_gfx_v9_hqd_load()
Damdgpu_amdkfd_gfx_v10_3.c239 CP_HQD_PQ_CONTROL, QUEUE_SIZE); in hqd_load_v10_3()
Dgfx_v9_0.c3347 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in gfx_v9_0_mqd_init()
3349 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in gfx_v9_0_mqd_init()
3352 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in gfx_v9_0_mqd_init()
3354 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v9_0_mqd_init()
3355 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); in gfx_v9_0_mqd_init()
3356 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v9_0_mqd_init()
3357 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in gfx_v9_0_mqd_init()
Dgfx_v8_0.c4490 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in gfx_v8_0_mqd_init()
4492 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in gfx_v8_0_mqd_init()
4495 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in gfx_v8_0_mqd_init()
4497 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v8_0_mqd_init()
4498 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); in gfx_v8_0_mqd_init()
4499 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v8_0_mqd_init()
4500 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in gfx_v8_0_mqd_init()
Dgfx_v11_0.c3826 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in gfx_v11_0_compute_mqd_init()
3828 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in gfx_v11_0_compute_mqd_init()
3830 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v11_0_compute_mqd_init()
3831 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); in gfx_v11_0_compute_mqd_init()
3832 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v11_0_compute_mqd_init()
3833 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in gfx_v11_0_compute_mqd_init()
Dgfx_v10_0.c6733 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in gfx_v10_0_compute_mqd_init()
6735 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in gfx_v10_0_compute_mqd_init()
6738 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in gfx_v10_0_compute_mqd_init()
6740 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v10_0_compute_mqd_init()
6741 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); in gfx_v10_0_compute_mqd_init()
6742 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v10_0_compute_mqd_init()
6743 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in gfx_v10_0_compute_mqd_init()
/linux-6.1.9/drivers/gpu/drm/radeon/
Dcikd.h1519 #define CP_HQD_PQ_CONTROL 0xC958 macro
Dcik.c4658 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL); in cik_cp_compute_resume()
4673 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); in cik_cp_compute_resume()