1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2018-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef HL_BOOT_IF_H 9 #define HL_BOOT_IF_H 10 11 #define LKD_HARD_RESET_MAGIC 0xED7BD694 /* deprecated - do not use */ 12 #define HL_POWER9_HOST_MAGIC 0x1DA30009 13 14 #define BOOT_FIT_SRAM_OFFSET 0x200000 15 16 #define VERSION_MAX_LEN 128 17 18 enum cpu_boot_err { 19 CPU_BOOT_ERR_DRAM_INIT_FAIL = 0, 20 CPU_BOOT_ERR_FIT_CORRUPTED = 1, 21 CPU_BOOT_ERR_TS_INIT_FAIL = 2, 22 CPU_BOOT_ERR_DRAM_SKIPPED = 3, 23 CPU_BOOT_ERR_BMC_WAIT_SKIPPED = 4, 24 CPU_BOOT_ERR_NIC_DATA_NOT_RDY = 5, 25 CPU_BOOT_ERR_NIC_FW_FAIL = 6, 26 CPU_BOOT_ERR_SECURITY_NOT_RDY = 7, 27 CPU_BOOT_ERR_SECURITY_FAIL = 8, 28 CPU_BOOT_ERR_EFUSE_FAIL = 9, 29 CPU_BOOT_ERR_PRI_IMG_VER_FAIL = 10, 30 CPU_BOOT_ERR_SEC_IMG_VER_FAIL = 11, 31 CPU_BOOT_ERR_PLL_FAIL = 12, 32 CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL = 13, 33 CPU_BOOT_ERR_BOOT_FW_CRIT_ERR = 18, 34 CPU_BOOT_ERR_BINNING_FAIL = 19, 35 CPU_BOOT_ERR_TPM_FAIL = 20, 36 CPU_BOOT_ERR_TMP_THRESH_INIT_FAIL = 21, 37 CPU_BOOT_ERR_EEPROM_FAIL = 22, 38 CPU_BOOT_ERR_ENABLED = 31, 39 CPU_BOOT_ERR_SCND_EN = 63, 40 CPU_BOOT_ERR_LAST = 64 /* we have 2 registers of 32 bits */ 41 }; 42 43 /* 44 * CPU error bits in BOOT_ERROR registers 45 * 46 * CPU_BOOT_ERR0_DRAM_INIT_FAIL DRAM initialization failed. 47 * DRAM is not reliable to use. 48 * 49 * CPU_BOOT_ERR0_FIT_CORRUPTED FIT data integrity verification of the 50 * image provided by the host has failed. 51 * 52 * CPU_BOOT_ERR0_TS_INIT_FAIL Thermal Sensor initialization failed. 53 * Boot continues as usual, but keep in 54 * mind this is a warning. 55 * 56 * CPU_BOOT_ERR0_DRAM_SKIPPED DRAM initialization has been skipped. 57 * Skipping DRAM initialization has been 58 * requested (e.g. strap, command, etc.) 59 * and FW skipped the DRAM initialization. 60 * Host can initialize the DRAM. 61 * 62 * CPU_BOOT_ERR0_BMC_WAIT_SKIPPED Waiting for BMC data will be skipped. 63 * Meaning the BMC data might not be 64 * available until reset. 65 * 66 * CPU_BOOT_ERR0_NIC_DATA_NOT_RDY NIC data from BMC is not ready. 67 * BMC has not provided the NIC data yet. 68 * Once provided this bit will be cleared. 69 * 70 * CPU_BOOT_ERR0_NIC_FW_FAIL NIC FW loading failed. 71 * The NIC FW loading and initialization 72 * failed. This means NICs are not usable. 73 * 74 * CPU_BOOT_ERR0_SECURITY_NOT_RDY Chip security initialization has been 75 * started, but is not ready yet - chip 76 * cannot be accessed. 77 * 78 * CPU_BOOT_ERR0_SECURITY_FAIL Security related tasks have failed. 79 * The tasks are security init (root of 80 * trust), boot authentication (chain of 81 * trust), data packets authentication. 82 * 83 * CPU_BOOT_ERR0_EFUSE_FAIL Reading from eFuse failed. 84 * The PCI device ID might be wrong. 85 * 86 * CPU_BOOT_ERR0_PRI_IMG_VER_FAIL Verification of primary image failed. 87 * It mean that ppboot checksum 88 * verification for the preboot primary 89 * image has failed to match expected 90 * checksum. Trying to program image again 91 * might solve this. 92 * 93 * CPU_BOOT_ERR0_SEC_IMG_VER_FAIL Verification of secondary image failed. 94 * It mean that ppboot checksum 95 * verification for the preboot secondary 96 * image has failed to match expected 97 * checksum. Trying to program image again 98 * might solve this. 99 * 100 * CPU_BOOT_ERR0_PLL_FAIL PLL settings failed, meaning that one 101 * of the PLLs remains in REF_CLK 102 * 103 * CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL Device is unusable and customer support 104 * should be contacted. 105 * 106 * CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR Critical error was detected during 107 * the execution of ppboot or preboot. 108 * for example: stack overflow. 109 * 110 * CPU_BOOT_ERR0_BINNING_FAIL Binning settings failed, meaning 111 * malfunctioning components might still be 112 * in use. 113 * 114 * CPU_BOOT_ERR0_TPM_FAIL TPM verification flow failed. 115 * 116 * CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL Failed to set threshold for tmperature 117 * sensor. 118 * 119 * CPU_BOOT_ERR_EEPROM_FAIL Failed reading EEPROM data. Defaults 120 * are used. 121 * 122 * CPU_BOOT_ERR0_ENABLED Error registers enabled. 123 * This is a main indication that the 124 * running FW populates the error 125 * registers. Meaning the error bits are 126 * not garbage, but actual error statuses. 127 */ 128 #define CPU_BOOT_ERR0_DRAM_INIT_FAIL (1 << CPU_BOOT_ERR_DRAM_INIT_FAIL) 129 #define CPU_BOOT_ERR0_FIT_CORRUPTED (1 << CPU_BOOT_ERR_FIT_CORRUPTED) 130 #define CPU_BOOT_ERR0_TS_INIT_FAIL (1 << CPU_BOOT_ERR_TS_INIT_FAIL) 131 #define CPU_BOOT_ERR0_DRAM_SKIPPED (1 << CPU_BOOT_ERR_DRAM_SKIPPED) 132 #define CPU_BOOT_ERR0_BMC_WAIT_SKIPPED (1 << CPU_BOOT_ERR_BMC_WAIT_SKIPPED) 133 #define CPU_BOOT_ERR0_NIC_DATA_NOT_RDY (1 << CPU_BOOT_ERR_NIC_DATA_NOT_RDY) 134 #define CPU_BOOT_ERR0_NIC_FW_FAIL (1 << CPU_BOOT_ERR_NIC_FW_FAIL) 135 #define CPU_BOOT_ERR0_SECURITY_NOT_RDY (1 << CPU_BOOT_ERR_SECURITY_NOT_RDY) 136 #define CPU_BOOT_ERR0_SECURITY_FAIL (1 << CPU_BOOT_ERR_SECURITY_FAIL) 137 #define CPU_BOOT_ERR0_EFUSE_FAIL (1 << CPU_BOOT_ERR_EFUSE_FAIL) 138 #define CPU_BOOT_ERR0_PRI_IMG_VER_FAIL (1 << CPU_BOOT_ERR_PRI_IMG_VER_FAIL) 139 #define CPU_BOOT_ERR0_SEC_IMG_VER_FAIL (1 << CPU_BOOT_ERR_SEC_IMG_VER_FAIL) 140 #define CPU_BOOT_ERR0_PLL_FAIL (1 << CPU_BOOT_ERR_PLL_FAIL) 141 #define CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL (1 << CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL) 142 #define CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR (1 << CPU_BOOT_ERR_BOOT_FW_CRIT_ERR) 143 #define CPU_BOOT_ERR0_BINNING_FAIL (1 << CPU_BOOT_ERR_BINNING_FAIL) 144 #define CPU_BOOT_ERR0_TPM_FAIL (1 << CPU_BOOT_ERR_TPM_FAIL) 145 #define CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL (1 << CPU_BOOT_ERR_TMP_THRESH_INIT_FAIL) 146 #define CPU_BOOT_ERR0_EEPROM_FAIL (1 << CPU_BOOT_ERR_EEPROM_FAIL) 147 #define CPU_BOOT_ERR0_ENABLED (1 << CPU_BOOT_ERR_ENABLED) 148 #define CPU_BOOT_ERR1_ENABLED (1 << CPU_BOOT_ERR_ENABLED) 149 150 enum cpu_boot_dev_sts { 151 CPU_BOOT_DEV_STS_SECURITY_EN = 0, 152 CPU_BOOT_DEV_STS_DEBUG_EN = 1, 153 CPU_BOOT_DEV_STS_WATCHDOG_EN = 2, 154 CPU_BOOT_DEV_STS_DRAM_INIT_EN = 3, 155 CPU_BOOT_DEV_STS_BMC_WAIT_EN = 4, 156 CPU_BOOT_DEV_STS_E2E_CRED_EN = 5, 157 CPU_BOOT_DEV_STS_HBM_CRED_EN = 6, 158 CPU_BOOT_DEV_STS_RL_EN = 7, 159 CPU_BOOT_DEV_STS_SRAM_SCR_EN = 8, 160 CPU_BOOT_DEV_STS_DRAM_SCR_EN = 9, 161 CPU_BOOT_DEV_STS_FW_HARD_RST_EN = 10, 162 CPU_BOOT_DEV_STS_PLL_INFO_EN = 11, 163 CPU_BOOT_DEV_STS_SP_SRAM_EN = 12, 164 CPU_BOOT_DEV_STS_CLK_GATE_EN = 13, 165 CPU_BOOT_DEV_STS_HBM_ECC_EN = 14, 166 CPU_BOOT_DEV_STS_PKT_PI_ACK_EN = 15, 167 CPU_BOOT_DEV_STS_FW_LD_COM_EN = 16, 168 CPU_BOOT_DEV_STS_FW_IATU_CONF_EN = 17, 169 CPU_BOOT_DEV_STS_FW_NIC_MAC_EN = 18, 170 CPU_BOOT_DEV_STS_DYN_PLL_EN = 19, 171 CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN = 20, 172 CPU_BOOT_DEV_STS_EQ_INDEX_EN = 21, 173 CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN = 22, 174 CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN = 23, 175 CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN = 24, 176 CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN = 25, 177 CPU_BOOT_DEV_STS_MAP_HWMON_EN = 26, 178 CPU_BOOT_DEV_STS_ENABLED = 31, 179 CPU_BOOT_DEV_STS_SCND_EN = 63, 180 CPU_BOOT_DEV_STS_LAST = 64 /* we have 2 registers of 32 bits */ 181 }; 182 183 /* 184 * BOOT DEVICE STATUS bits in BOOT_DEVICE_STS registers 185 * 186 * CPU_BOOT_DEV_STS0_SECURITY_EN Security is Enabled. 187 * This is an indication for security 188 * enabled in FW, which means that 189 * all conditions for security are met: 190 * device is indicated as security enabled, 191 * registers are protected, and device 192 * uses keys for image verification. 193 * Initialized in: preboot 194 * 195 * CPU_BOOT_DEV_STS0_DEBUG_EN Debug is enabled. 196 * Enabled when JTAG or DEBUG is enabled 197 * in FW. 198 * Initialized in: preboot 199 * 200 * CPU_BOOT_DEV_STS0_WATCHDOG_EN Watchdog is enabled. 201 * Watchdog is enabled in FW. 202 * Initialized in: preboot 203 * 204 * CPU_BOOT_DEV_STS0_DRAM_INIT_EN DRAM initialization is enabled. 205 * DRAM initialization has been done in FW. 206 * Initialized in: u-boot 207 * 208 * CPU_BOOT_DEV_STS0_BMC_WAIT_EN Waiting for BMC data enabled. 209 * If set, it means that during boot, 210 * FW waited for BMC data. 211 * Initialized in: u-boot 212 * 213 * CPU_BOOT_DEV_STS0_E2E_CRED_EN E2E credits initialized. 214 * FW initialized E2E credits. 215 * Initialized in: u-boot 216 * 217 * CPU_BOOT_DEV_STS0_HBM_CRED_EN HBM credits initialized. 218 * FW initialized HBM credits. 219 * Initialized in: u-boot 220 * 221 * CPU_BOOT_DEV_STS0_RL_EN Rate limiter initialized. 222 * FW initialized rate limiter. 223 * Initialized in: u-boot 224 * 225 * CPU_BOOT_DEV_STS0_SRAM_SCR_EN SRAM scrambler enabled. 226 * FW initialized SRAM scrambler. 227 * Initialized in: linux 228 * 229 * CPU_BOOT_DEV_STS0_DRAM_SCR_EN DRAM scrambler enabled. 230 * FW initialized DRAM scrambler. 231 * Initialized in: u-boot 232 * 233 * CPU_BOOT_DEV_STS0_FW_HARD_RST_EN FW hard reset procedure is enabled. 234 * FW has the hard reset procedure 235 * implemented. This means that FW will 236 * perform hard reset procedure on 237 * receiving the halt-machine event. 238 * Initialized in: preboot, u-boot, linux 239 * 240 * CPU_BOOT_DEV_STS0_PLL_INFO_EN FW retrieval of PLL info is enabled. 241 * Initialized in: linux 242 * 243 * CPU_BOOT_DEV_STS0_SP_SRAM_EN SP SRAM is initialized and available 244 * for use. 245 * Initialized in: preboot 246 * 247 * CPU_BOOT_DEV_STS0_CLK_GATE_EN Clock Gating enabled. 248 * FW initialized Clock Gating. 249 * Initialized in: preboot 250 * 251 * CPU_BOOT_DEV_STS0_HBM_ECC_EN HBM ECC handling Enabled. 252 * FW handles HBM ECC indications. 253 * Initialized in: linux 254 * 255 * CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN Packets ack value used in the armcpd 256 * is set to the PI counter. 257 * Initialized in: linux 258 * 259 * CPU_BOOT_DEV_STS0_FW_LD_COM_EN Flexible FW loading communication 260 * protocol is enabled. 261 * Initialized in: preboot 262 * 263 * CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN FW iATU configuration is enabled. 264 * This bit if set, means the iATU has been 265 * configured and is ready for use. 266 * Initialized in: ppboot 267 * 268 * CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN NIC MAC channels init is done by FW and 269 * any access to them is done via the FW. 270 * Initialized in: linux 271 * 272 * CPU_BOOT_DEV_STS0_DYN_PLL_EN Dynamic PLL configuration is enabled. 273 * FW sends to host a bitmap of supported 274 * PLLs. 275 * Initialized in: linux 276 * 277 * CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN GIC access permission only from 278 * previleged entity. FW sets this status 279 * bit for host. If this bit is set then 280 * GIC can not be accessed from host. 281 * Initialized in: linux 282 * 283 * CPU_BOOT_DEV_STS0_EQ_INDEX_EN Event Queue (EQ) index is a running 284 * index for each new event sent to host. 285 * This is used as a method in host to 286 * identify that the waiting event in 287 * queue is actually a new event which 288 * was not served before. 289 * Initialized in: linux 290 * 291 * CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN Use multiple scratchpad interfaces to 292 * prevent IRQs overriding each other. 293 * Initialized in: linux 294 * 295 * CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN 296 * NIC STAT and XPCS91 access is restricted 297 * and is done via FW only. 298 * Initialized in: linux 299 * 300 * CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN 301 * NIC STAT get all is supported. 302 * Initialized in: linux 303 * 304 * CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN 305 * F/W checks if the device is idle by reading defined set 306 * of registers. It returns a bitmask of all the engines, 307 * where a bit is set if the engine is not idle. 308 * Initialized in: linux 309 * 310 * CPU_BOOT_DEV_STS0_MAP_HWMON_EN 311 * If set, means f/w supports proprietary 312 * HWMON enum mapping to cpucp enums. 313 * Initialized in: linux 314 * 315 * CPU_BOOT_DEV_STS0_ENABLED Device status register enabled. 316 * This is a main indication that the 317 * running FW populates the device status 318 * register. Meaning the device status 319 * bits are not garbage, but actual 320 * statuses. 321 * Initialized in: preboot 322 * 323 */ 324 #define CPU_BOOT_DEV_STS0_SECURITY_EN (1 << CPU_BOOT_DEV_STS_SECURITY_EN) 325 #define CPU_BOOT_DEV_STS0_DEBUG_EN (1 << CPU_BOOT_DEV_STS_DEBUG_EN) 326 #define CPU_BOOT_DEV_STS0_WATCHDOG_EN (1 << CPU_BOOT_DEV_STS_WATCHDOG_EN) 327 #define CPU_BOOT_DEV_STS0_DRAM_INIT_EN (1 << CPU_BOOT_DEV_STS_DRAM_INIT_EN) 328 #define CPU_BOOT_DEV_STS0_BMC_WAIT_EN (1 << CPU_BOOT_DEV_STS_BMC_WAIT_EN) 329 #define CPU_BOOT_DEV_STS0_E2E_CRED_EN (1 << CPU_BOOT_DEV_STS_E2E_CRED_EN) 330 #define CPU_BOOT_DEV_STS0_HBM_CRED_EN (1 << CPU_BOOT_DEV_STS_HBM_CRED_EN) 331 #define CPU_BOOT_DEV_STS0_RL_EN (1 << CPU_BOOT_DEV_STS_RL_EN) 332 #define CPU_BOOT_DEV_STS0_SRAM_SCR_EN (1 << CPU_BOOT_DEV_STS_SRAM_SCR_EN) 333 #define CPU_BOOT_DEV_STS0_DRAM_SCR_EN (1 << CPU_BOOT_DEV_STS_DRAM_SCR_EN) 334 #define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN (1 << CPU_BOOT_DEV_STS_FW_HARD_RST_EN) 335 #define CPU_BOOT_DEV_STS0_PLL_INFO_EN (1 << CPU_BOOT_DEV_STS_PLL_INFO_EN) 336 #define CPU_BOOT_DEV_STS0_SP_SRAM_EN (1 << CPU_BOOT_DEV_STS_SP_SRAM_EN) 337 #define CPU_BOOT_DEV_STS0_CLK_GATE_EN (1 << CPU_BOOT_DEV_STS_CLK_GATE_EN) 338 #define CPU_BOOT_DEV_STS0_HBM_ECC_EN (1 << CPU_BOOT_DEV_STS_HBM_ECC_EN) 339 #define CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN (1 << CPU_BOOT_DEV_STS_PKT_PI_ACK_EN) 340 #define CPU_BOOT_DEV_STS0_FW_LD_COM_EN (1 << CPU_BOOT_DEV_STS_FW_LD_COM_EN) 341 #define CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN (1 << CPU_BOOT_DEV_STS_FW_IATU_CONF_EN) 342 #define CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_MAC_EN) 343 #define CPU_BOOT_DEV_STS0_DYN_PLL_EN (1 << CPU_BOOT_DEV_STS_DYN_PLL_EN) 344 #define CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN (1 << CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN) 345 #define CPU_BOOT_DEV_STS0_EQ_INDEX_EN (1 << CPU_BOOT_DEV_STS_EQ_INDEX_EN) 346 #define CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN (1 << CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN) 347 #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN) 348 #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN) 349 #define CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN (1 << CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN) 350 #define CPU_BOOT_DEV_STS0_MAP_HWMON_EN (1 << CPU_BOOT_DEV_STS_MAP_HWMON_EN) 351 #define CPU_BOOT_DEV_STS0_ENABLED (1 << CPU_BOOT_DEV_STS_ENABLED) 352 #define CPU_BOOT_DEV_STS1_ENABLED (1 << CPU_BOOT_DEV_STS_ENABLED) 353 354 enum cpu_boot_status { 355 CPU_BOOT_STATUS_NA = 0, /* Default value after reset of chip */ 356 CPU_BOOT_STATUS_IN_WFE = 1, 357 CPU_BOOT_STATUS_DRAM_RDY = 2, 358 CPU_BOOT_STATUS_SRAM_AVAIL = 3, 359 CPU_BOOT_STATUS_IN_BTL = 4, /* BTL is H/W FSM */ 360 CPU_BOOT_STATUS_IN_PREBOOT = 5, 361 CPU_BOOT_STATUS_IN_SPL, /* deprecated - not reported */ 362 CPU_BOOT_STATUS_IN_UBOOT = 7, 363 CPU_BOOT_STATUS_DRAM_INIT_FAIL, /* deprecated - will be removed */ 364 CPU_BOOT_STATUS_FIT_CORRUPTED, /* deprecated - will be removed */ 365 /* U-Boot console prompt activated, commands are not processed */ 366 CPU_BOOT_STATUS_UBOOT_NOT_READY = 10, 367 /* Finished NICs init, reported after DRAM and NICs */ 368 CPU_BOOT_STATUS_NIC_FW_RDY = 11, 369 CPU_BOOT_STATUS_TS_INIT_FAIL, /* deprecated - will be removed */ 370 CPU_BOOT_STATUS_DRAM_SKIPPED, /* deprecated - will be removed */ 371 CPU_BOOT_STATUS_BMC_WAITING_SKIPPED, /* deprecated - will be removed */ 372 /* Last boot loader progress status, ready to receive commands */ 373 CPU_BOOT_STATUS_READY_TO_BOOT = 15, 374 /* Internal Boot finished, ready for boot-fit */ 375 CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT = 16, 376 /* Internal Security has been initialized, device can be accessed */ 377 CPU_BOOT_STATUS_SECURITY_READY = 17, 378 }; 379 380 enum kmd_msg { 381 KMD_MSG_NA = 0, 382 KMD_MSG_GOTO_WFE, 383 KMD_MSG_FIT_RDY, 384 KMD_MSG_SKIP_BMC, 385 RESERVED, 386 KMD_MSG_RST_DEV, 387 KMD_MSG_LAST 388 }; 389 390 enum cpu_msg_status { 391 CPU_MSG_CLR = 0, 392 CPU_MSG_OK, 393 CPU_MSG_ERR, 394 }; 395 396 /* communication registers mapping - consider ABI when changing */ 397 struct cpu_dyn_regs { 398 __le32 cpu_pq_base_addr_low; 399 __le32 cpu_pq_base_addr_high; 400 __le32 cpu_pq_length; 401 __le32 cpu_pq_init_status; 402 __le32 cpu_eq_base_addr_low; 403 __le32 cpu_eq_base_addr_high; 404 __le32 cpu_eq_length; 405 __le32 cpu_eq_ci; 406 __le32 cpu_cq_base_addr_low; 407 __le32 cpu_cq_base_addr_high; 408 __le32 cpu_cq_length; 409 __le32 cpu_pf_pq_pi; 410 __le32 cpu_boot_dev_sts0; 411 __le32 cpu_boot_dev_sts1; 412 __le32 cpu_boot_err0; 413 __le32 cpu_boot_err1; 414 __le32 cpu_boot_status; 415 __le32 fw_upd_sts; 416 __le32 fw_upd_cmd; 417 __le32 fw_upd_pending_sts; 418 __le32 fuse_ver_offset; 419 __le32 preboot_ver_offset; 420 __le32 uboot_ver_offset; 421 __le32 hw_state; 422 __le32 kmd_msg_to_cpu; 423 __le32 cpu_cmd_status_to_host; 424 __le32 gic_host_pi_upd_irq; 425 __le32 gic_tpc_qm_irq_ctrl; 426 __le32 gic_mme_qm_irq_ctrl; 427 __le32 gic_dma_qm_irq_ctrl; 428 __le32 gic_nic_qm_irq_ctrl; 429 __le32 gic_dma_core_irq_ctrl; 430 __le32 gic_host_halt_irq; 431 __le32 gic_host_ints_irq; 432 __le32 gic_host_soft_rst_irq; 433 __le32 gic_rot_qm_irq_ctrl; 434 __le32 cpu_rst_status; 435 __le32 eng_arc_irq_ctrl; 436 __le32 reserved1[20]; /* reserve for future use */ 437 }; 438 439 /* TODO: remove the desc magic after the code is updated to use message */ 440 /* HCDM - Habana Communications Descriptor Magic */ 441 #define HL_COMMS_DESC_MAGIC 0x4843444D 442 #define HL_COMMS_DESC_VER 1 443 444 /* HCMv - Habana Communications Message + header version */ 445 #define HL_COMMS_MSG_MAGIC_VALUE 0x48434D00 446 #define HL_COMMS_MSG_MAGIC_MASK 0xFFFFFF00 447 #define HL_COMMS_MSG_MAGIC_VER_MASK 0xFF 448 449 #define HL_COMMS_MSG_MAGIC_VER(ver) (HL_COMMS_MSG_MAGIC_VALUE | \ 450 ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK)) 451 #define HL_COMMS_MSG_MAGIC_V0 HL_COMMS_DESC_MAGIC 452 #define HL_COMMS_MSG_MAGIC_V1 HL_COMMS_MSG_MAGIC_VER(1) 453 454 #define HL_COMMS_MSG_MAGIC HL_COMMS_MSG_MAGIC_V1 455 456 #define HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC(magic) \ 457 (((magic) & HL_COMMS_MSG_MAGIC_MASK) == \ 458 HL_COMMS_MSG_MAGIC_VALUE) 459 460 #define HL_COMMS_MSG_MAGIC_VALIDATE_VERSION(magic, ver) \ 461 (((magic) & HL_COMMS_MSG_MAGIC_VER_MASK) >= \ 462 ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK)) 463 464 #define HL_COMMS_MSG_MAGIC_VALIDATE(magic, ver) \ 465 (HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC((magic)) && \ 466 HL_COMMS_MSG_MAGIC_VALIDATE_VERSION((magic), (ver))) 467 468 enum comms_msg_type { 469 HL_COMMS_DESC_TYPE = 0, 470 HL_COMMS_RESET_CAUSE_TYPE = 1, 471 HL_COMMS_FW_CFG_SKIP_TYPE = 2, 472 HL_COMMS_BINNING_CONF_TYPE = 3, 473 }; 474 475 /* 476 * Binning information shared between LKD and FW 477 * @tpc_mask - TPC binning information 478 * @dec_mask - Decoder binning information 479 * @hbm_mask - HBM binning information 480 * @edma_mask - EDMA binning information 481 * @mme_mask_l - MME binning information lower 32 482 * @mme_mask_h - MME binning information upper 32 483 * @reserved - reserved field for 64 bit alignment 484 */ 485 struct lkd_fw_binning_info { 486 __le64 tpc_mask; 487 __le32 dec_mask; 488 __le32 hbm_mask; 489 __le32 edma_mask; 490 __le32 mme_mask_l; 491 __le32 mme_mask_h; 492 __le32 reserved; 493 }; 494 495 /* TODO: remove this struct after the code is updated to use message */ 496 /* this is the comms descriptor header - meta data */ 497 struct comms_desc_header { 498 __le32 magic; /* magic for validation */ 499 __le32 crc32; /* CRC32 of the descriptor w/o header */ 500 __le16 size; /* size of the descriptor w/o header */ 501 __u8 version; /* descriptor version */ 502 __u8 reserved[5]; /* pad to 64 bit */ 503 }; 504 505 /* this is the comms message header - meta data */ 506 struct comms_msg_header { 507 __le32 magic; /* magic for validation */ 508 __le32 crc32; /* CRC32 of the message w/o header */ 509 __le16 size; /* size of the message w/o header */ 510 __u8 version; /* message payload version */ 511 __u8 type; /* message type */ 512 __u8 reserved[4]; /* pad to 64 bit */ 513 }; 514 515 /* this is the main FW descriptor - consider ABI when changing */ 516 struct lkd_fw_comms_desc { 517 struct comms_desc_header header; 518 struct cpu_dyn_regs cpu_dyn_regs; 519 char fuse_ver[VERSION_MAX_LEN]; 520 char cur_fw_ver[VERSION_MAX_LEN]; 521 /* can be used for 1 more version w/o ABI change */ 522 char reserved0[VERSION_MAX_LEN]; 523 __le64 img_addr; /* address for next FW component load */ 524 }; 525 526 enum comms_reset_cause { 527 HL_RESET_CAUSE_UNKNOWN = 0, 528 HL_RESET_CAUSE_HEARTBEAT = 1, 529 HL_RESET_CAUSE_TDR = 2, 530 }; 531 532 /* TODO: remove define after struct name is aligned on all projects */ 533 #define lkd_msg_comms lkd_fw_comms_msg 534 535 /* this is the comms message descriptor */ 536 struct lkd_fw_comms_msg { 537 struct comms_msg_header header; 538 /* union for future expantions of new messages */ 539 union { 540 struct { 541 struct cpu_dyn_regs cpu_dyn_regs; 542 char fuse_ver[VERSION_MAX_LEN]; 543 char cur_fw_ver[VERSION_MAX_LEN]; 544 /* can be used for 1 more version w/o ABI change */ 545 char reserved0[VERSION_MAX_LEN]; 546 /* address for next FW component load */ 547 __le64 img_addr; 548 }; 549 struct { 550 __u8 reset_cause; 551 }; 552 struct { 553 __u8 fw_cfg_skip; /* 1 - skip, 0 - don't skip */ 554 }; 555 struct lkd_fw_binning_info binning_info; 556 }; 557 }; 558 559 /* 560 * LKD commands: 561 * 562 * COMMS_NOOP Used to clear the command register and no actual 563 * command is send. 564 * 565 * COMMS_CLR_STS Clear status command - FW should clear the 566 * status register. Used for synchronization 567 * between the commands as part of the race free 568 * protocol. 569 * 570 * COMMS_RST_STATE Reset the current communication state which is 571 * kept by FW for proper responses. 572 * Should be used in the beginning of the 573 * communication cycle to clean any leftovers from 574 * previous communication attempts. 575 * 576 * COMMS_PREP_DESC Prepare descriptor for setting up the 577 * communication and other dynamic data: 578 * struct lkd_fw_comms_desc. 579 * This command has a parameter stating the next FW 580 * component size, so the FW can actually prepare a 581 * space for it and in the status response provide 582 * the descriptor offset. The Offset of the next FW 583 * data component is a part of the descriptor 584 * structure. 585 * 586 * COMMS_DATA_RDY The FW data has been uploaded and is ready for 587 * validation. 588 * 589 * COMMS_EXEC Execute the next FW component. 590 * 591 * COMMS_RST_DEV Reset the device. 592 * 593 * COMMS_GOTO_WFE Execute WFE command. Allowed only on non-secure 594 * devices. 595 * 596 * COMMS_SKIP_BMC Perform actions required for BMC-less servers. 597 * Do not wait for BMC response. 598 * 599 * COMMS_PREP_DESC_ELBI Same as COMMS_PREP_DESC only that the memory 600 * space is allocated in a ELBI access only 601 * address range. 602 * 603 */ 604 enum comms_cmd { 605 COMMS_NOOP = 0, 606 COMMS_CLR_STS = 1, 607 COMMS_RST_STATE = 2, 608 COMMS_PREP_DESC = 3, 609 COMMS_DATA_RDY = 4, 610 COMMS_EXEC = 5, 611 COMMS_RST_DEV = 6, 612 COMMS_GOTO_WFE = 7, 613 COMMS_SKIP_BMC = 8, 614 COMMS_PREP_DESC_ELBI = 10, 615 COMMS_INVLD_LAST 616 }; 617 618 #define COMMS_COMMAND_SIZE_SHIFT 0 619 #define COMMS_COMMAND_SIZE_MASK 0x1FFFFFF 620 #define COMMS_COMMAND_CMD_SHIFT 27 621 #define COMMS_COMMAND_CMD_MASK 0xF8000000 622 623 /* 624 * LKD command to FW register structure 625 * @size - FW component size 626 * @cmd - command from enum comms_cmd 627 */ 628 struct comms_command { 629 union { /* bit fields are only for FW use */ 630 struct { 631 u32 size :25; /* 32MB max. */ 632 u32 reserved :2; 633 enum comms_cmd cmd :5; /* 32 commands */ 634 }; 635 __le32 val; 636 }; 637 }; 638 639 /* 640 * FW status 641 * 642 * COMMS_STS_NOOP Used to clear the status register and no actual 643 * status is provided. 644 * 645 * COMMS_STS_ACK Command has been received and recognized. 646 * 647 * COMMS_STS_OK Command execution has finished successfully. 648 * 649 * COMMS_STS_ERR Command execution was unsuccessful and resulted 650 * in error. 651 * 652 * COMMS_STS_VALID_ERR FW validation has failed. 653 * 654 * COMMS_STS_TIMEOUT_ERR Command execution has timed out. 655 */ 656 enum comms_sts { 657 COMMS_STS_NOOP = 0, 658 COMMS_STS_ACK = 1, 659 COMMS_STS_OK = 2, 660 COMMS_STS_ERR = 3, 661 COMMS_STS_VALID_ERR = 4, 662 COMMS_STS_TIMEOUT_ERR = 5, 663 COMMS_STS_INVLD_LAST 664 }; 665 666 /* RAM types for FW components loading - defines the base address */ 667 enum comms_ram_types { 668 COMMS_SRAM = 0, 669 COMMS_DRAM = 1, 670 }; 671 672 #define COMMS_STATUS_OFFSET_SHIFT 0 673 #define COMMS_STATUS_OFFSET_MASK 0x03FFFFFF 674 #define COMMS_STATUS_OFFSET_ALIGN_SHIFT 2 675 #define COMMS_STATUS_RAM_TYPE_SHIFT 26 676 #define COMMS_STATUS_RAM_TYPE_MASK 0x0C000000 677 #define COMMS_STATUS_STATUS_SHIFT 28 678 #define COMMS_STATUS_STATUS_MASK 0xF0000000 679 680 /* 681 * FW status to LKD register structure 682 * @offset - an offset from the base of the ram_type shifted right by 683 * 2 bits (always aligned to 32 bits). 684 * Allows a maximum addressable offset of 256MB from RAM base. 685 * Example: for real offset in RAM of 0x800000 (8MB), the value 686 * in offset field is (0x800000 >> 2) = 0x200000. 687 * @ram_type - the RAM type that should be used for offset from 688 * enum comms_ram_types 689 * @status - status from enum comms_sts 690 */ 691 struct comms_status { 692 union { /* bit fields are only for FW use */ 693 struct { 694 u32 offset :26; 695 enum comms_ram_types ram_type :2; 696 enum comms_sts status :4; /* 16 statuses */ 697 }; 698 __le32 val; 699 }; 700 }; 701 702 #endif /* HL_BOOT_IF_H */ 703