1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */ 3 4 #ifndef __RTL8188E_SPEC_H__ 5 #define __RTL8188E_SPEC_H__ 6 7 /* 8192C Regsiter offset definition */ 8 9 #define HAL_PS_TIMER_INT_DELAY 50 /* 50 microseconds */ 10 #define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */ 11 12 /* 8188E PKT_BUFF_ACCESS_CTRL value */ 13 #define TXPKT_BUF_SELECT 0x69 14 #define RXPKT_BUF_SELECT 0xA5 15 #define DISABLE_TRXPKT_BUF_ACCESS 0x0 16 17 /* 0x0000h ~ 0x00FFh System Configuration */ 18 #define REG_SYS_ISO_CTRL 0x0000 19 #define REG_SYS_FUNC_EN 0x0002 20 #define REG_APS_FSMCO 0x0004 21 #define REG_SYS_CLKR 0x0008 22 #define REG_9346CR 0x000A 23 #define REG_EE_VPD 0x000C 24 #define REG_AFE_MISC 0x0010 25 #define REG_SPS0_CTRL 0x0011 26 #define REG_SPS_OCP_CFG 0x0018 27 #define REG_RSV_CTRL 0x001C 28 #define REG_RF_CTRL 0x001F 29 #define REG_LDOA15_CTRL 0x0020 30 #define REG_LDOV12D_CTRL 0x0021 31 #define REG_LDOHCI12_CTRL 0x0022 32 #define REG_LPLDO_CTRL 0x0023 33 #define REG_AFE_XTAL_CTRL 0x0024 34 #define REG_AFE_PLL_CTRL 0x0028 35 #define REG_APE_PLL_CTRL_EXT 0x002c 36 #define REG_EFUSE_CTRL 0x0030 37 #define REG_EFUSE_TEST 0x0034 38 #define REG_GPIO_MUXCFG 0x0040 39 #define REG_GPIO_IO_SEL 0x0042 40 #define REG_MAC_PINMUX_CFG 0x0043 41 #define REG_GPIO_PIN_CTRL 0x0044 42 #define REG_GPIO_INTM 0x0048 43 #define REG_LEDCFG0 0x004C 44 #define REG_LEDCFG1 0x004D 45 #define REG_LEDCFG2 0x004E 46 #define REG_LEDCFG3 0x004F 47 #define REG_FSIMR 0x0050 48 #define REG_FSISR 0x0054 49 #define REG_HSIMR 0x0058 50 #define REG_HSISR 0x005c 51 #define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS 52 * Multi-Function GPIO Pin Control. */ 53 #define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS 54 * Multi-Function GPIO Select. */ 55 #define REG_BB_PAD_CTRL 0x0064 56 #define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS 57 * Multi-Function control source. */ 58 #define REG_GPIO_OUTPUT 0x006c 59 #define REG_AFE_XTAL_CTRL_EXT 0x0078 /* RTL8188E */ 60 #define REG_XCK_OUT_CTRL 0x007c /* RTL8188E */ 61 #define REG_MCUFWDL 0x0080 62 #define REG_WOL_EVENT 0x0081 /* RTL8188E */ 63 #define REG_MCUTSTCFG 0x0084 64 #define REG_HMEBOX_E0 0x0088 65 #define REG_HMEBOX_E1 0x008A 66 #define REG_HMEBOX_E2 0x008C 67 #define REG_HMEBOX_E3 0x008E 68 #define REG_HMEBOX_EXT_0 0x01F0 69 #define REG_HMEBOX_EXT_1 0x01F4 70 #define REG_HMEBOX_EXT_2 0x01F8 71 #define REG_HMEBOX_EXT_3 0x01FC 72 #define REG_HIMR_88E 0x00B0 73 #define REG_HISR_88E 0x00B4 74 #define REG_HIMRE_88E 0x00B8 75 #define REG_HISRE_88E 0x00BC 76 #define REG_EFUSE_ACCESS 0x00CF /* Efuse access protection 77 * for RTL8723 */ 78 #define REG_BIST_SCAN 0x00D0 79 #define REG_BIST_RPT 0x00D4 80 #define REG_BIST_ROM_RPT 0x00D8 81 #define REG_USB_SIE_INTF 0x00E0 82 #define REG_PCIE_MIO_INTF 0x00E4 83 #define REG_PCIE_MIO_INTD 0x00E8 84 #define REG_HPON_FSM 0x00EC 85 #define REG_SYS_CFG 0x00F0 86 #define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */ 87 #define REG_TYPE_ID 0x00FC 88 89 #define REG_MAC_PHY_CTRL_NORMAL 0x00f8 90 91 /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 92 #define REG_CR 0x0100 93 #define REG_PBP 0x0104 94 #define REG_PKT_BUFF_ACCESS_CTRL 0x0106 95 #define REG_TRXDMA_CTRL 0x010C 96 #define REG_TRXFF_BNDY 0x0114 97 #define REG_TRXFF_STATUS 0x0118 98 #define REG_RXFF_PTR 0x011C 99 /* define REG_HIMR 0x0120 */ 100 /* define REG_HISR 0x0124 */ 101 #define REG_HIMRE 0x0128 102 #define REG_HISRE 0x012C 103 #define REG_CPWM 0x012F 104 #define REG_FWIMR 0x0130 105 #define REG_FTIMR 0x0138 106 #define REG_FWISR 0x0134 107 #define REG_PKTBUF_DBG_CTRL 0x0140 108 #define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) 109 #define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) 110 #define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) 111 #define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) 112 #define REG_PKTBUF_DBG_DATA_L 0x0144 113 #define REG_PKTBUF_DBG_DATA_H 0x0148 114 115 #define REG_TC0_CTRL 0x0150 116 #define REG_TC1_CTRL 0x0154 117 #define REG_TC2_CTRL 0x0158 118 #define REG_TC3_CTRL 0x015C 119 #define REG_TC4_CTRL 0x0160 120 #define REG_TCUNIT_BASE 0x0164 121 #define REG_MBIST_START 0x0174 122 #define REG_MBIST_DONE 0x0178 123 #define REG_MBIST_FAIL 0x017C 124 #define REG_32K_CTRL 0x0194 /* RTL8188E */ 125 #define REG_C2HEVT_MSG_NORMAL 0x01A0 126 #define REG_C2HEVT_CLEAR 0x01AF 127 #define REG_MCUTST_1 0x01c0 128 #define REG_FMETHR 0x01C8 129 #define REG_HMETFR 0x01CC 130 #define REG_HMEBOX_0 0x01D0 131 #define REG_HMEBOX_1 0x01D4 132 #define REG_HMEBOX_2 0x01D8 133 #define REG_HMEBOX_3 0x01DC 134 135 #define REG_LLT_INIT 0x01E0 136 137 /* 0x0200h ~ 0x027Fh TXDMA Configuration */ 138 #define REG_RQPN 0x0200 139 #define REG_FIFOPAGE 0x0204 140 #define REG_TDECTRL 0x0208 141 #define REG_TXDMA_OFFSET_CHK 0x020C 142 #define REG_TXDMA_STATUS 0x0210 143 #define REG_RQPN_NPQ 0x0214 144 145 /* 0x0280h ~ 0x02FFh RXDMA Configuration */ 146 #define REG_RXDMA_AGG_PG_TH 0x0280 147 #define REG_RXPKT_NUM 0x0284 148 #define REG_RXDMA_STATUS 0x0288 149 150 /* 0x0300h ~ 0x03FFh PCIe */ 151 #define REG_PCIE_CTRL_REG 0x0300 152 #define REG_INT_MIG 0x0304 /* Interrupt Migration */ 153 #define REG_BCNQ_DESA 0x0308 /* TX Beacon Descr Address */ 154 #define REG_HQ_DESA 0x0310 /* TX High Queue Descr Addr */ 155 #define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descr Addr*/ 156 #define REG_VOQ_DESA 0x0320 /* TX VO Queue Descr Addr */ 157 #define REG_VIQ_DESA 0x0328 /* TX VI Queue Descr Addr */ 158 #define REG_BEQ_DESA 0x0330 /* TX BE Queue Descr Addr */ 159 #define REG_BKQ_DESA 0x0338 /* TX BK Queue Descr Addr */ 160 #define REG_RX_DESA 0x0340 /* RX Queue Descr Addr */ 161 #define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */ 162 #define REG_DBG_SEL 0x0360 /* Debug Selection Register */ 163 #define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */ 164 #define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */ 165 #define REG_WATCH_DOG 0x0368 166 167 /* RTL8723 series ------------------------------ */ 168 #define REG_PCIE_HISR 0x03A0 169 170 /* spec version 11 */ 171 /* 0x0400h ~ 0x047Fh Protocol Configuration */ 172 #define REG_VOQ_INFORMATION 0x0400 173 #define REG_VIQ_INFORMATION 0x0404 174 #define REG_BEQ_INFORMATION 0x0408 175 #define REG_BKQ_INFORMATION 0x040C 176 #define REG_MGQ_INFORMATION 0x0410 177 #define REG_HGQ_INFORMATION 0x0414 178 #define REG_BCNQ_INFORMATION 0x0418 179 #define REG_TXPKT_EMPTY 0x041A 180 181 #define REG_CPU_MGQ_INFORMATION 0x041C 182 #define REG_FWHW_TXQ_CTRL 0x0420 183 #define REG_HWSEQ_CTRL 0x0423 184 #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 185 #define REG_TXPKTBUF_MGQ_BDNY 0x0425 186 #define REG_LIFETIME_EN 0x0426 187 #define REG_MULTI_BCNQ_OFFSET 0x0427 188 #define REG_SPEC_SIFS 0x0428 189 #define REG_RL 0x042A 190 #define REG_DARFRC 0x0430 191 #define REG_RARFRC 0x0438 192 #define REG_RRSR 0x0440 193 #define REG_ARFR0 0x0444 194 #define REG_ARFR1 0x0448 195 #define REG_ARFR2 0x044C 196 #define REG_ARFR3 0x0450 197 #define REG_AGGLEN_LMT 0x0458 198 #define REG_AMPDU_MIN_SPACE 0x045C 199 #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 200 #define REG_FAST_EDCA_CTRL 0x0460 201 #define REG_RD_RESP_PKT_TH 0x0463 202 #define REG_INIRTS_RATE_SEL 0x0480 203 /* define REG_INIDATA_RATE_SEL 0x0484 */ 204 #define REG_POWER_STATUS 0x04A4 205 #define REG_POWER_STAGE1 0x04B4 206 #define REG_POWER_STAGE2 0x04B8 207 #define REG_PKT_VO_VI_LIFE_TIME 0x04C0 208 #define REG_PKT_BE_BK_LIFE_TIME 0x04C2 209 #define REG_STBC_SETTING 0x04C4 210 #define REG_PROT_MODE_CTRL 0x04C8 211 #define REG_MAX_AGGR_NUM 0x04CA 212 #define REG_RTS_MAX_AGGR_NUM 0x04CB 213 #define REG_BAR_MODE_CTRL 0x04CC 214 #define REG_RA_TRY_RATE_AGG_LMT 0x04CF 215 #define REG_EARLY_MODE_CONTROL 0x4D0 216 #define REG_NQOS_SEQ 0x04DC 217 #define REG_QOS_SEQ 0x04DE 218 #define REG_NEED_CPU_HANDLE 0x04E0 219 #define REG_PKT_LOSE_RPT 0x04E1 220 #define REG_PTCL_ERR_STATUS 0x04E2 221 #define REG_TX_RPT_CTRL 0x04EC 222 #define REG_TX_RPT_TIME 0x04F0 /* 2 byte */ 223 #define REG_DUMMY 0x04FC 224 225 /* 0x0500h ~ 0x05FFh EDCA Configuration */ 226 #define REG_EDCA_VO_PARAM 0x0500 227 #define REG_EDCA_VI_PARAM 0x0504 228 #define REG_EDCA_BE_PARAM 0x0508 229 #define REG_EDCA_BK_PARAM 0x050C 230 #define REG_BCNTCFG 0x0510 231 #define REG_PIFS 0x0512 232 #define REG_RDG_PIFS 0x0513 233 #define REG_SIFS_CTX 0x0514 234 #define REG_SIFS_TRX 0x0516 235 #define REG_TSFTR_SYN_OFFSET 0x0518 236 #define REG_AGGR_BREAK_TIME 0x051A 237 #define REG_SLOT 0x051B 238 #define REG_TX_PTCL_CTRL 0x0520 239 #define REG_TXPAUSE 0x0522 240 #define REG_DIS_TXREQ_CLR 0x0523 241 #define REG_RD_CTRL 0x0524 242 /* Format for offset 540h-542h: */ 243 /* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting 244 * beacon content before TBTT. */ 245 /* [7:4]: Reserved. */ 246 /* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding 247 * to send the beacon packet. */ 248 /* [23:20]: Reserved */ 249 /* Description: */ 250 /* | */ 251 /* |<--Setup--|--Hold------------>| */ 252 /* --------------|---------------------- */ 253 /* | */ 254 /* TBTT */ 255 /* Note: We cannot update beacon content to HW or send any AC packets during 256 * the time between Setup and Hold. */ 257 #define REG_TBTT_PROHIBIT 0x0540 258 #define REG_RD_NAV_NXT 0x0544 259 #define REG_NAV_PROT_LEN 0x0546 260 #define REG_BCN_CTRL 0x0550 261 #define REG_BCN_CTRL_1 0x0551 262 #define REG_MBID_NUM 0x0552 263 #define REG_DUAL_TSF_RST 0x0553 264 #define REG_BCN_INTERVAL 0x0554 265 #define REG_DRVERLYINT 0x0558 266 #define REG_BCNDMATIM 0x0559 267 #define REG_ATIMWND 0x055A 268 #define REG_BCN_MAX_ERR 0x055D 269 #define REG_RXTSF_OFFSET_CCK 0x055E 270 #define REG_RXTSF_OFFSET_OFDM 0x055F 271 #define REG_TSFTR 0x0560 272 #define REG_TSFTR1 0x0568 273 #define REG_ATIMWND_1 0x0570 274 #define REG_PSTIMER 0x0580 275 #define REG_TIMER0 0x0584 276 #define REG_TIMER1 0x0588 277 #define REG_ACMHWCTRL 0x05C0 278 279 /* define REG_FW_TSF_SYNC_CNT 0x04A0 */ 280 #define REG_FW_RESET_TSF_CNT_1 0x05FC 281 #define REG_FW_RESET_TSF_CNT_0 0x05FD 282 #define REG_FW_BCN_DIS_CNT 0x05FE 283 284 /* 0x0600h ~ 0x07FFh WMAC Configuration */ 285 #define REG_APSD_CTRL 0x0600 286 #define REG_BWOPMODE 0x0603 287 #define REG_TCR 0x0604 288 #define REG_RCR 0x0608 289 #define REG_RX_PKT_LIMIT 0x060C 290 #define REG_RX_DLK_TIME 0x060D 291 #define REG_RX_DRVINFO_SZ 0x060F 292 293 #define REG_MACID 0x0610 294 #define REG_BSSID 0x0618 295 #define REG_MAR 0x0620 296 #define REG_MBIDCAMCFG 0x0628 297 298 #define REG_USTIME_EDCA 0x0638 299 #define REG_MAC_SPEC_SIFS 0x063A 300 301 /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ 302 /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 303 #define REG_R2T_SIFS 0x063C 304 /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 305 #define REG_T2T_SIFS 0x063E 306 #define REG_ACKTO 0x0640 307 #define REG_CTS2TO 0x0641 308 #define REG_EIFS 0x0642 309 310 /* RXERR_RPT */ 311 #define RXERR_TYPE_OFDM_PPDU 0 312 #define RXERR_TYPE_OFDM_false_ALARM 1 313 #define RXERR_TYPE_OFDM_MPDU_OK 2 314 #define RXERR_TYPE_OFDM_MPDU_FAIL 3 315 #define RXERR_TYPE_CCK_PPDU 4 316 #define RXERR_TYPE_CCK_false_ALARM 5 317 #define RXERR_TYPE_CCK_MPDU_OK 6 318 #define RXERR_TYPE_CCK_MPDU_FAIL 7 319 #define RXERR_TYPE_HT_PPDU 8 320 #define RXERR_TYPE_HT_false_ALARM 9 321 #define RXERR_TYPE_HT_MPDU_TOTAL 10 322 #define RXERR_TYPE_HT_MPDU_OK 11 323 #define RXERR_TYPE_HT_MPDU_FAIL 12 324 #define RXERR_TYPE_RX_FULL_DROP 15 325 326 #define RXERR_COUNTER_MASK 0xFFFFF 327 #define RXERR_RPT_RST BIT(27) 328 #define _RXERR_RPT_SEL(type) ((type) << 28) 329 330 /* Note: */ 331 /* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. 332 * The default value is always too small, but the WiFi TestPlan test 333 * by 25,000 microseconds of NAV through sending CTS in the air. 334 * We must update this value greater than 25,000 microseconds to pass 335 * the item. The offset of NAV_UPPER in 8192C Spec is incorrect, and 336 * the offset should be 0x0652. */ 337 #define REG_NAV_UPPER 0x0652 /* unit of 128 */ 338 339 /* WMA, BA, CCX */ 340 /* define REG_NAV_CTRL 0x0650 */ 341 #define REG_BACAMCMD 0x0654 342 #define REG_BACAMCONTENT 0x0658 343 #define REG_LBDLY 0x0660 344 #define REG_FWDLY 0x0661 345 #define REG_RXERR_RPT 0x0664 346 #define REG_WMAC_TRXPTCL_CTL 0x0668 347 348 /* Security */ 349 #define REG_CAMCMD 0x0670 350 #define REG_CAMWRITE 0x0674 351 #define REG_CAMREAD 0x0678 352 #define REG_CAMDBG 0x067C 353 #define REG_SECCFG 0x0680 354 355 /* Power */ 356 #define REG_WOW_CTRL 0x0690 357 #define REG_PS_RX_INFO 0x0692 358 #define REG_UAPSD_TID 0x0693 359 #define REG_WKFMCAM_CMD 0x0698 360 #define REG_WKFMCAM_NUM_88E 0x698 361 #define REG_RXFLTMAP0 0x06A0 362 #define REG_RXFLTMAP1 0x06A2 363 #define REG_RXFLTMAP2 0x06A4 364 #define REG_BCN_PSR_RPT 0x06A8 365 #define REG_BT_COEX_TABLE 0x06C0 366 367 /* Hardware Port 2 */ 368 #define REG_MACID1 0x0700 369 #define REG_BSSID1 0x0708 370 371 /* 0xFE00h ~ 0xFE55h USB Configuration */ 372 #define REG_USB_INFO 0xFE17 373 #define REG_USB_SPECIAL_OPTION 0xFE55 374 #define REG_USB_DMA_AGG_TO 0xFE5B 375 #define REG_USB_AGG_TO 0xFE5C 376 #define REG_USB_AGG_TH 0xFE5D 377 378 /* For normal chip */ 379 #define REG_NORMAL_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ 380 #define REG_NORMAL_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ 381 #define REG_NORMAL_SIE_OPTIONAL 0xFE64 382 #define REG_NORMAL_SIE_EP 0xFE65 /* 0xFE65~0xFE67 */ 383 #define REG_NORMAL_SIE_PHY 0xFE68 /* 0xFE68~0xFE6B */ 384 #define REG_NORMAL_SIE_OPTIONAL2 0xFE6C 385 #define REG_NORMAL_SIE_GPS_EP 0xFE6D /* 0xFE6D, for RTL8723 only. */ 386 #define REG_NORMAL_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ 387 #define REG_NORMAL_SIE_STRING 0xFE80 /* 0xFE80~0xFEDF */ 388 389 /* TODO: use these definition when using REG_xxx naming rule. */ 390 /* NOTE: DO NOT Remove these definition. Use later. */ 391 392 #define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */ 393 #define EFUSE_TEST REG_EFUSE_TEST /* E-Fuse Test. */ 394 #define MSR (REG_CR + 2) /* Media Status reg */ 395 #define ISR REG_HISR_88E 396 /* Timing Sync Function Timer Register. */ 397 #define TSFR REG_TSFTR 398 399 #define PBP REG_PBP 400 401 /* Redifine MACID register, to compatible prior ICs. */ 402 /* MAC ID Register, Offset 0x0050-0x0053 */ 403 #define IDR0 REG_MACID 404 /* MAC ID Register, Offset 0x0054-0x0055 */ 405 #define IDR4 (REG_MACID + 4) 406 407 /* 9. Security Control Registers (Offset: ) */ 408 /* IN 8190 Data Sheet is called CAMcmd */ 409 #define RWCAM REG_CAMCMD 410 /* Software write CAM input content */ 411 #define WCAMI REG_CAMWRITE 412 /* Software read/write CAM config */ 413 #define RCAMO REG_CAMREAD 414 #define CAMDBG REG_CAMDBG 415 /* Security Configuration Register */ 416 #define SECR REG_SECCFG 417 418 /* Unused register */ 419 #define UnusedRegister 0x1BF 420 #define DCAM UnusedRegister 421 #define PSR UnusedRegister 422 #define BBAddr UnusedRegister 423 #define PhyDataR UnusedRegister 424 425 /* Min Spacing related settings. */ 426 #define MAX_MSS_DENSITY_2T 0x13 427 #define MAX_MSS_DENSITY_1T 0x0A 428 429 /* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */ 430 #define GPIOSEL_GPIO 0 431 #define GPIOSEL_ENBT BIT(5) 432 433 /* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */ 434 /* GPIO pins input value */ 435 #define GPIO_IN REG_GPIO_PIN_CTRL 436 /* GPIO pins output value */ 437 #define GPIO_OUT (REG_GPIO_PIN_CTRL+1) 438 /* GPIO pins output enable when a bit is set to "1"; otherwise, 439 * input is configured. */ 440 #define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) 441 #define GPIO_MOD (REG_GPIO_PIN_CTRL+3) 442 443 /* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */ 444 #define HSIMR_GPIO12_0_INT_EN BIT(0) 445 #define HSIMR_SPS_OCP_INT_EN BIT(5) 446 #define HSIMR_RON_INT_EN BIT(6) 447 #define HSIMR_PDN_INT_EN BIT(7) 448 #define HSIMR_GPIO9_INT_EN BIT(25) 449 450 /* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ 451 #define HSISR_GPIO12_0_INT BIT(0) 452 #define HSISR_SPS_OCP_INT BIT(5) 453 #define HSISR_RON_INT_EN BIT(6) 454 #define HSISR_PDNINT BIT(7) 455 #define HSISR_GPIO9_INT BIT(25) 456 457 /* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */ 458 /* 459 Network Type 460 00: No link 461 01: Link in ad hoc network 462 10: Link in infrastructure network 463 11: AP mode 464 Default: 00b. 465 */ 466 #define MSR_NOLINK 0x00 467 #define MSR_ADHOC 0x01 468 #define MSR_INFRA 0x02 469 #define MSR_AP 0x03 470 471 /* 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) */ 472 /* IOL config for REG_FDHM0(Reg0x88) */ 473 #define CMD_INIT_LLT BIT(0) 474 #define CMD_READ_EFUSE_MAP BIT(1) 475 #define CMD_EFUSE_PATCH BIT(2) 476 #define CMD_IOCONFIG BIT(3) 477 #define CMD_INIT_LLT_ERR BIT(4) 478 #define CMD_READ_EFUSE_MAP_ERR BIT(5) 479 #define CMD_EFUSE_PATCH_ERR BIT(6) 480 #define CMD_IOCONFIG_ERR BIT(7) 481 482 /* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */ 483 /* 8192C Response Rate Set Register (offset 0x181, 24bits) */ 484 #define RRSR_1M BIT(0) 485 #define RRSR_2M BIT(1) 486 #define RRSR_5_5M BIT(2) 487 #define RRSR_11M BIT(3) 488 #define RRSR_6M BIT(4) 489 #define RRSR_9M BIT(5) 490 #define RRSR_12M BIT(6) 491 #define RRSR_18M BIT(7) 492 #define RRSR_24M BIT(8) 493 #define RRSR_36M BIT(9) 494 #define RRSR_48M BIT(10) 495 #define RRSR_54M BIT(11) 496 #define RRSR_MCS0 BIT(12) 497 #define RRSR_MCS1 BIT(13) 498 #define RRSR_MCS2 BIT(14) 499 #define RRSR_MCS3 BIT(15) 500 #define RRSR_MCS4 BIT(16) 501 #define RRSR_MCS5 BIT(17) 502 #define RRSR_MCS6 BIT(18) 503 #define RRSR_MCS7 BIT(19) 504 505 /* 8192C Response Rate Set Register (offset 0x1BF, 8bits) */ 506 /* WOL bit information */ 507 #define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0) 508 #define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1) 509 510 /* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */ 511 #define BW_OPMODE_20MHZ BIT(2) 512 513 /* 8192C CAM Config Setting (offset 0x250, 1 byte) */ 514 #define CAM_VALID BIT(15) 515 #define CAM_NOTVALID 0x0000 516 #define CAM_USEDK BIT(5) 517 518 #define CAM_CONTENT_COUNT 8 519 520 #define CAM_NONE 0x0 521 #define CAM_WEP40 0x01 522 #define CAM_TKIP 0x02 523 #define CAM_AES 0x04 524 #define CAM_WEP104 0x05 525 #define CAM_SMS4 0x6 526 527 #define TOTAL_CAM_ENTRY 32 528 #define HALF_CAM_ENTRY 16 529 530 #define CAM_CONFIG_USEDK true 531 #define CAM_CONFIG_NO_USEDK false 532 533 #define CAM_WRITE BIT(16) 534 #define CAM_READ 0x00000000 535 #define CAM_POLLINIG BIT(31) 536 537 #define SCR_UseDK 0x01 538 #define SCR_TxSecEnable 0x02 539 #define SCR_RxSecEnable 0x04 540 541 /* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */ 542 #define WOW_PMEN BIT(0) /* Power management Enable. */ 543 #define WOW_WOMEN BIT(1) /* WoW function on or off. */ 544 #define WOW_MAGIC BIT(2) /* Magic packet */ 545 #define WOW_UWF BIT(3) /* Unicast Wakeup frame. */ 546 547 /* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */ 548 /* 8188 IMR/ISR bits */ 549 #define IMR_DISABLED_88E 0x0 550 /* IMR DW0(0x0060-0063) Bit 0-31 */ 551 #define IMR_TXCCK_88E BIT(30) /* TXRPT interrupt when CCX bit of the packet is set */ 552 #define IMR_PSTIMEOUT_88E BIT(29) /* Power Save Time Out Interrupt */ 553 #define IMR_GTINT4_88E BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ 554 #define IMR_GTINT3_88E BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ 555 #define IMR_TBDER_88E BIT(26) /* Transmit Beacon0 Error */ 556 #define IMR_TBDOK_88E BIT(25) /* Transmit Beacon0 OK */ 557 #define IMR_TSF_BIT32_TOGGLE_88E BIT(24) /* TSF Timer BIT32 toggle indication interrupt */ 558 #define IMR_BCNDMAINT0_88E BIT(20) /* Beacon DMA Interrupt 0 */ 559 #define IMR_BCNDERR0_88E BIT(16) /* Beacon Queue DMA Error 0 */ 560 #define IMR_HSISR_IND_ON_INT_88E BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 561 #define IMR_BCNDMAINT_E_88E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ 562 #define IMR_ATIMEND_88E BIT(12) /* CTWidnow End or ATIM Window End */ 563 #define IMR_HISR1_IND_INT_88E BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ 564 #define IMR_C2HCMD_88E BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ 565 #define IMR_CPWM2_88E BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ 566 #define IMR_CPWM_88E BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ 567 #define IMR_HIGHDOK_88E BIT(7) /* High Queue DMA OK */ 568 #define IMR_MGNTDOK_88E BIT(6) /* Management Queue DMA OK */ 569 #define IMR_BKDOK_88E BIT(5) /* AC_BK DMA OK */ 570 #define IMR_BEDOK_88E BIT(4) /* AC_BE DMA OK */ 571 #define IMR_VIDOK_88E BIT(3) /* AC_VI DMA OK */ 572 #define IMR_VODOK_88E BIT(2) /* AC_VO DMA OK */ 573 #define IMR_RDU_88E BIT(1) /* Rx Descriptor Unavailable */ 574 #define IMR_ROK_88E BIT(0) /* Receive DMA OK */ 575 576 /* IMR DW1(0x00B4-00B7) Bit 0-31 */ 577 #define IMR_BCNDMAINT7_88E BIT(27) /* Beacon DMA Interrupt 7 */ 578 #define IMR_BCNDMAINT6_88E BIT(26) /* Beacon DMA Interrupt 6 */ 579 #define IMR_BCNDMAINT5_88E BIT(25) /* Beacon DMA Interrupt 5 */ 580 #define IMR_BCNDMAINT4_88E BIT(24) /* Beacon DMA Interrupt 4 */ 581 #define IMR_BCNDMAINT3_88E BIT(23) /* Beacon DMA Interrupt 3 */ 582 #define IMR_BCNDMAINT2_88E BIT(22) /* Beacon DMA Interrupt 2 */ 583 #define IMR_BCNDMAINT1_88E BIT(21) /* Beacon DMA Interrupt 1 */ 584 #define IMR_BCNDERR7_88E BIT(20) /* Beacon DMA Error Int 7 */ 585 #define IMR_BCNDERR6_88E BIT(19) /* Beacon DMA Error Int 6 */ 586 #define IMR_BCNDERR5_88E BIT(18) /* Beacon DMA Error Int 5 */ 587 #define IMR_BCNDERR4_88E BIT(17) /* Beacon DMA Error Int 4 */ 588 #define IMR_BCNDERR3_88E BIT(16) /* Beacon DMA Error Int 3 */ 589 #define IMR_BCNDERR2_88E BIT(15) /* Beacon DMA Error Int 2 */ 590 #define IMR_BCNDERR1_88E BIT(14) /* Beacon DMA Error Int 1 */ 591 #define IMR_ATIMEND_E_88E BIT(13) /* ATIM Window End Ext for Win7 */ 592 #define IMR_TXERR_88E BIT(11) /* Tx Err Flag Int Status, write 1 clear. */ 593 #define IMR_RXERR_88E BIT(10) /* Rx Err Flag INT Status, Write 1 clear */ 594 #define IMR_TXFOVW_88E BIT(9) /* Transmit FIFO Overflow */ 595 #define IMR_RXFOVW_88E BIT(8) /* Receive FIFO Overflow */ 596 597 #define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF /* The value when the NIC is unplugged for PCI. */ 598 599 /* 8192C EFUSE */ 600 #define HWSET_MAX_SIZE 256 601 #define HWSET_MAX_SIZE_88E 512 602 603 /*=================================================================== 604 ===================================================================== 605 Here the register defines are for 92C. When the define is as same with 92C, 606 we will use the 92C's define for the consistency 607 So the following defines for 92C is not entire!!!!!! 608 ===================================================================== 609 =====================================================================*/ 610 /* 611 Based on Datasheet V33---090401 612 Register Summary 613 Current IOREG MAP 614 0x0000h ~ 0x00FFh System Configuration (256 Bytes) 615 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) 616 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) 617 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) 618 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) 619 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) 620 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) 621 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) 622 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) 623 */ 624 /* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */ 625 /* Note: */ 626 /* The bits of stopping AC(VO/VI/BE/BK) queue in datasheet 627 * RTL8192S/RTL8192C are wrong, */ 628 /* the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, 629 * and BK - Bit3. */ 630 /* 8723 and 88E may be not correct either in the earlier version. */ 631 #define StopBecon BIT(6) 632 #define StopHigh BIT(5) 633 #define StopMgt BIT(4) 634 #define StopBK BIT(3) 635 #define StopBE BIT(2) 636 #define StopVI BIT(1) 637 #define StopVO BIT(0) 638 639 /* 8192C (RCR) Receive Configuration Register(Offset 0x608, 32 bits) */ 640 #define RCR_APPFCS BIT(31) /* WMAC append FCS after payload */ 641 #define RCR_APP_MIC BIT(30) 642 #define RCR_APP_PHYSTS BIT(28) 643 #define RCR_APP_ICV BIT(29) 644 #define RCR_APP_PHYST_RXFF BIT(28) 645 #define RCR_APP_BA_SSN BIT(27) /* Accept BA SSN */ 646 #define RCR_ENMBID BIT(24) /* Enable Multiple BssId. */ 647 #define RCR_LSIGEN BIT(23) 648 #define RCR_MFBEN BIT(22) 649 #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ 650 #define RCR_AMF BIT(13) /* Accept management type frame */ 651 #define RCR_ACF BIT(12) /* Accept control type frame */ 652 #define RCR_ADF BIT(11) /* Accept data type frame */ 653 #define RCR_AICV BIT(9) /* Accept ICV error packet */ 654 #define RCR_ACRC32 BIT(8) /* Accept CRC32 error packet */ 655 #define RCR_CBSSID_BCN BIT(7) /* Accept BSSID match packet 656 * (Rx beacon, probe rsp) */ 657 #define RCR_CBSSID_DATA BIT(6) /* Accept BSSID match (Data)*/ 658 #define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match */ 659 #define RCR_APWRMGT BIT(5) /* Accept power management pkt*/ 660 #define RCR_ADD3 BIT(4) /* Accept address 3 match pkt */ 661 #define RCR_AB BIT(3) /* Accept broadcast packet */ 662 #define RCR_AM BIT(2) /* Accept multicast packet */ 663 #define RCR_APM BIT(1) /* Accept physical match pkt */ 664 #define RCR_AAP BIT(0) /* Accept all unicast packet */ 665 #define RCR_MXDMA_OFFSET 8 666 #define RCR_FIFO_OFFSET 13 667 668 /* 0xFE00h ~ 0xFE55h USB Configuration */ 669 #define REG_USB_INFO 0xFE17 670 #define REG_USB_SPECIAL_OPTION 0xFE55 671 #define REG_USB_DMA_AGG_TO 0xFE5B 672 #define REG_USB_AGG_TO 0xFE5C 673 #define REG_USB_AGG_TH 0xFE5D 674 675 #define REG_USB_HRPWM 0xFE58 676 #define REG_USB_HCPWM 0xFE57 677 /* 8192C Regsiter Bit and Content definition */ 678 /* 0x0000h ~ 0x00FFh System Configuration */ 679 680 /* 2 SYS_ISO_CTRL */ 681 #define ISO_MD2PP BIT(0) 682 #define ISO_UA2USB BIT(1) 683 #define ISO_UD2CORE BIT(2) 684 #define ISO_PA2PCIE BIT(3) 685 #define ISO_PD2CORE BIT(4) 686 #define ISO_IP2MAC BIT(5) 687 #define ISO_DIOP BIT(6) 688 #define ISO_DIOE BIT(7) 689 #define ISO_EB2CORE BIT(8) 690 #define ISO_DIOR BIT(9) 691 #define PWC_EV12V BIT(15) 692 693 /* 2 SYS_FUNC_EN */ 694 #define FEN_BBRSTB BIT(0) 695 #define FEN_BB_GLB_RSTn BIT(1) 696 #define FEN_USBA BIT(2) 697 #define FEN_UPLL BIT(3) 698 #define FEN_USBD BIT(4) 699 #define FEN_DIO_PCIE BIT(5) 700 #define FEN_PCIEA BIT(6) 701 #define FEN_PPLL BIT(7) 702 #define FEN_PCIED BIT(8) 703 #define FEN_DIOE BIT(9) 704 #define FEN_CPUEN BIT(10) 705 #define FEN_DCORE BIT(11) 706 #define FEN_ELDR BIT(12) 707 #define FEN_DIO_RF BIT(13) 708 #define FEN_HWPDN BIT(14) 709 #define FEN_MREGEN BIT(15) 710 711 /* 2 APS_FSMCO */ 712 #define PFM_LDALL BIT(0) 713 #define PFM_ALDN BIT(1) 714 #define PFM_LDKP BIT(2) 715 #define PFM_WOWL BIT(3) 716 #define EnPDN BIT(4) 717 #define PDN_PL BIT(5) 718 #define APFM_ONMAC BIT(8) 719 #define APFM_OFF BIT(9) 720 #define APFM_RSM BIT(10) 721 #define AFSM_HSUS BIT(11) 722 #define AFSM_PCIE BIT(12) 723 #define APDM_MAC BIT(13) 724 #define APDM_HOST BIT(14) 725 #define APDM_HPDN BIT(15) 726 #define RDY_MACON BIT(16) 727 #define SUS_HOST BIT(17) 728 #define ROP_ALD BIT(20) 729 #define ROP_PWR BIT(21) 730 #define ROP_SPS BIT(22) 731 #define SOP_MRST BIT(25) 732 #define SOP_FUSE BIT(26) 733 #define SOP_ABG BIT(27) 734 #define SOP_AMB BIT(28) 735 #define SOP_RCK BIT(29) 736 #define SOP_A8M BIT(30) 737 #define XOP_BTCK BIT(31) 738 739 /* 2 SYS_CLKR */ 740 #define ANAD16V_EN BIT(0) 741 #define ANA8M BIT(1) 742 #define MACSLP BIT(4) 743 #define LOADER_CLK_EN BIT(5) 744 745 /* 2 9346CR */ 746 747 #define BOOT_FROM_EEPROM BIT(4) 748 #define EEPROM_EN BIT(5) 749 750 /* 2 SPS0_CTRL */ 751 752 /* 2 SPS_OCP_CFG */ 753 754 /* 2 RF_CTRL */ 755 #define RF_EN BIT(0) 756 #define RF_RSTB BIT(1) 757 #define RF_SDMRSTB BIT(2) 758 759 /* 2 LDOV12D_CTRL */ 760 #define LDV12_EN BIT(0) 761 #define LDV12_SDBY BIT(1) 762 #define LPLDO_HSM BIT(2) 763 #define LPLDO_LSM_DIS BIT(3) 764 #define _LDV12_VADJ(x) (((x) & 0xF) << 4) 765 766 /* 2EFUSE_CTRL */ 767 #define ALD_EN BIT(18) 768 #define EF_PD BIT(19) 769 #define EF_FLAG BIT(31) 770 771 /* 2 EFUSE_TEST (For RTL8723 partially) */ 772 #define EF_TRPT BIT(7) 773 /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ 774 #define EF_CELL_SEL (BIT(8)|BIT(9)) 775 #define LDOE25_EN BIT(31) 776 #define EFUSE_SEL(x) (((x) & 0x3) << 8) 777 #define EFUSE_SEL_MASK 0x300 778 #define EFUSE_WIFI_SEL_0 0x0 779 #define EFUSE_BT_SEL_0 0x1 780 #define EFUSE_BT_SEL_1 0x2 781 #define EFUSE_BT_SEL_2 0x3 782 783 #define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */ 784 #define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */ 785 786 /* 2 8051FWDL */ 787 /* 2 MCUFWDL */ 788 #define MCUFWDL_EN BIT(0) 789 #define MCUFWDL_RDY BIT(1) 790 #define FWDL_CHKSUM_RPT BIT(2) 791 #define MACINI_RDY BIT(3) 792 #define BBINI_RDY BIT(4) 793 #define RFINI_RDY BIT(5) 794 #define WINTINI_RDY BIT(6) 795 #define RAM_DL_SEL BIT(7) /* 1:RAM, 0:ROM */ 796 #define ROM_DLEN BIT(19) 797 #define CPRST BIT(23) 798 799 /* 2 REG_SYS_CFG */ 800 #define XCLK_VLD BIT(0) 801 #define ACLK_VLD BIT(1) 802 #define UCLK_VLD BIT(2) 803 #define PCLK_VLD BIT(3) 804 #define PCIRSTB BIT(4) 805 #define V15_VLD BIT(5) 806 #define SW_OFFLOAD_EN BIT(7) 807 #define SIC_IDLE BIT(8) 808 #define BD_MAC2 BIT(9) 809 #define BD_MAC1 BIT(10) 810 #define IC_MACPHY_MODE BIT(11) 811 #define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) 812 #define BT_FUNC BIT(16) 813 #define VENDOR_ID BIT(19) 814 #define PAD_HWPD_IDN BIT(22) 815 #define TRP_VAUX_EN BIT(23) /* RTL ID */ 816 #define TRP_BT_EN BIT(24) 817 #define BD_PKG_SEL BIT(25) 818 #define BD_HCI_SEL BIT(26) 819 #define TYPE_ID BIT(27) 820 821 #define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */ 822 #define CHIP_VER_RTL_SHIFT 12 823 824 /* 2REG_GPIO_OUTSTS (For RTL8723 only) */ 825 #define EFS_HCI_SEL (BIT(0)|BIT(1)) 826 #define PAD_HCI_SEL (BIT(2)|BIT(3)) 827 #define HCI_SEL (BIT(4)|BIT(5)) 828 #define PKG_SEL_HCI BIT(6) 829 #define FEN_GPS BIT(7) 830 #define FEN_BT BIT(8) 831 #define FEN_WL BIT(9) 832 #define FEN_PCI BIT(10) 833 #define FEN_USB BIT(11) 834 #define BTRF_HWPDN_N BIT(12) 835 #define WLRF_HWPDN_N BIT(13) 836 #define PDN_BT_N BIT(14) 837 #define PDN_GPS_N BIT(15) 838 #define BT_CTL_HWPDN BIT(16) 839 #define GPS_CTL_HWPDN BIT(17) 840 #define PPHY_SUSB BIT(20) 841 #define UPHY_SUSB BIT(21) 842 #define PCI_SUSEN BIT(22) 843 #define USB_SUSEN BIT(23) 844 #define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) 845 846 /* 2SYS_CFG */ 847 #define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */ 848 849 /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 850 851 /* 2 Function Enable Registers */ 852 /* 2 CR */ 853 854 #define HCI_TXDMA_EN BIT(0) 855 #define HCI_RXDMA_EN BIT(1) 856 #define TXDMA_EN BIT(2) 857 #define RXDMA_EN BIT(3) 858 #define PROTOCOL_EN BIT(4) 859 #define SCHEDULE_EN BIT(5) 860 #define MACTXEN BIT(6) 861 #define MACRXEN BIT(7) 862 #define ENSWBCN BIT(8) 863 #define ENSEC BIT(9) 864 #define CALTMR_EN BIT(10) /* 32k CAL TMR enable */ 865 866 /* Network type */ 867 #define _NETTYPE(x) (((x) & 0x3) << 16) 868 #define MASK_NETTYPE 0x30000 869 #define NT_NO_LINK 0x0 870 #define NT_LINK_AD_HOC 0x1 871 #define NT_LINK_AP 0x2 872 #define NT_AS_AP 0x3 873 874 /* 2 PBP - Page Size Register */ 875 #define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 876 #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 877 #define _PSRX_MASK 0xF 878 #define _PSTX_MASK 0xF0 879 #define _PSRX(x) (x) 880 #define _PSTX(x) ((x) << 4) 881 882 #define PBP_128 0x1 883 884 /* 2 TX/RXDMA */ 885 #define RXDMA_ARBBW_EN BIT(0) 886 #define RXSHFT_EN BIT(1) 887 #define RXDMA_AGG_EN BIT(2) 888 #define QS_VO_QUEUE BIT(8) 889 #define QS_VI_QUEUE BIT(9) 890 #define QS_BE_QUEUE BIT(10) 891 #define QS_BK_QUEUE BIT(11) 892 #define QS_MANAGER_QUEUE BIT(12) 893 #define QS_HIGH_QUEUE BIT(13) 894 895 #define HQSEL_VOQ BIT(0) 896 #define HQSEL_VIQ BIT(1) 897 #define HQSEL_BEQ BIT(2) 898 #define HQSEL_BKQ BIT(3) 899 #define HQSEL_MGTQ BIT(4) 900 #define HQSEL_HIQ BIT(5) 901 902 /* For normal driver, 0x10C */ 903 #define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 904 #define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 905 #define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 906 #define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) 907 #define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) 908 #define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) 909 910 #define QUEUE_LOW 1 911 #define QUEUE_NORMAL 2 912 #define QUEUE_HIGH 3 913 914 /* 2 TRXFF_BNDY */ 915 916 /* 2 LLT_INIT */ 917 #define _LLT_NO_ACTIVE 0x0 918 #define _LLT_WRITE_ACCESS 0x1 919 #define _LLT_READ_ACCESS 0x2 920 921 #define _LLT_INIT_DATA(x) ((x) & 0xFF) 922 #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 923 #define _LLT_OP(x) (((x) & 0x3) << 30) 924 #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 925 926 /* 0x0200h ~ 0x027Fh TXDMA Configuration */ 927 928 #define NUM_HQ 0x29 929 930 #define LD_RQPN BIT(31) 931 932 /* 2TDECTRL */ 933 #define BCN_VALID BIT(16) 934 #define BCN_HEAD(x) (((x) & 0xFF) << 8) 935 #define BCN_HEAD_MASK 0xFF00 936 937 /* 2 TDECTL */ 938 #define BLK_DESC_NUM_SHIFT 4 939 #define BLK_DESC_NUM_MASK 0xF 940 941 /* 2 TXDMA_OFFSET_CHK */ 942 #define DROP_DATA_EN BIT(9) 943 944 /* 0x0280h ~ 0x028Bh RX DMA Configuration */ 945 946 /* REG_RXDMA_CONTROL, 0x0286h */ 947 948 /* 2 REG_RXPKT_NUM, 0x0284 */ 949 #define RXPKT_RELEASE_POLL BIT(16) 950 #define RXDMA_IDLE BIT(17) 951 #define RW_RELEASE_EN BIT(18) 952 953 /* 0x0400h ~ 0x047Fh Protocol Configuration */ 954 /* 2 FWHW_TXQ_CTRL */ 955 #define EN_AMPDU_RTY_NEW BIT(7) 956 957 /* 2 SPEC SIFS */ 958 #define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 959 #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 960 961 /* 2 RL */ 962 #define RETRY_LIMIT_SHORT_SHIFT 8 963 #define RETRY_LIMIT_LONG_SHIFT 0 964 965 /* 0x0500h ~ 0x05FFh EDCA Configuration */ 966 967 /* 2 EDCA setting */ 968 #define AC_PARAM_TXOP_LIMIT_OFFSET 16 969 #define AC_PARAM_ECW_MAX_OFFSET 12 970 #define AC_PARAM_ECW_MIN_OFFSET 8 971 #define AC_PARAM_AIFS_OFFSET 0 972 973 #define _LRL(x) ((x) & 0x3F) 974 #define _SRL(x) (((x) & 0x3F) << 8) 975 976 /* 2 BCN_CTRL */ 977 #define EN_MBSSID BIT(1) 978 #define EN_TXBCN_RPT BIT(2) 979 #define EN_BCN_FUNCTION BIT(3) 980 #define DIS_TSF_UPDATE BIT(3) 981 982 /* The same function but different bit field. */ 983 #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 984 #define DIS_TSF_UDT0_TEST_CHIP BIT(5) 985 #define STOP_BCNQ BIT(6) 986 987 /* 2 ACMHWCTRL */ 988 #define ACMHW_BEQEN BIT(1) 989 #define ACMHW_VIQEN BIT(2) 990 #define ACMHW_VOQEN BIT(3) 991 992 /* 0x0600h ~ 0x07FFh WMAC Configuration */ 993 /* 2APSD_CTRL */ 994 #define APSDOFF BIT(6) 995 #define APSDOFF_STATUS BIT(7) 996 997 #define RATE_BITMAP_ALL 0xFFFFF 998 999 /* Only use CCK 1M rate for ACK */ 1000 #define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 1001 1002 /* 2 TCR */ 1003 #define TSFRST BIT(0) 1004 #define DIS_GCLK BIT(1) 1005 #define PAD_SEL BIT(2) 1006 #define PWR_ST BIT(6) 1007 #define PWRBIT_OW_EN BIT(7) 1008 #define ACRC BIT(8) 1009 #define CFENDFORM BIT(9) 1010 #define ICV BIT(10) 1011 1012 /* 2 RCR */ 1013 #define AAP BIT(0) 1014 #define APM BIT(1) 1015 #define AM BIT(2) 1016 #define AB BIT(3) 1017 #define ADD3 BIT(4) 1018 #define APWRMGT BIT(5) 1019 #define CBSSID BIT(6) 1020 #define CBSSID_DATA BIT(6) 1021 #define CBSSID_BCN BIT(7) 1022 #define ACRC32 BIT(8) 1023 #define AICV BIT(9) 1024 #define ADF BIT(11) 1025 #define ACF BIT(12) 1026 #define AMF BIT(13) 1027 #define HTC_LOC_CTRL BIT(14) 1028 #define UC_DATA_EN BIT(16) 1029 #define BM_DATA_EN BIT(17) 1030 #define MFBEN BIT(22) 1031 #define LSIGEN BIT(23) 1032 #define EnMBID BIT(24) 1033 #define APP_BASSN BIT(27) 1034 #define APP_PHYSTS BIT(28) 1035 #define APP_ICV BIT(29) 1036 #define APP_MIC BIT(30) 1037 #define APP_FCS BIT(31) 1038 1039 /* 2 SECCFG */ 1040 #define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */ 1041 #define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */ 1042 #define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */ 1043 #define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */ 1044 #define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */ 1045 #define SCR_NoSKMC BIT(5) /* No Key Search Multicast */ 1046 #define SCR_TXBCUSEDK BIT(6) /* Force Tx Bcast pkt Use Default Key */ 1047 #define SCR_RXBCUSEDK BIT(7) /* Force Rx Bcast pkt Use Default Key */ 1048 1049 /* 0xFE00h ~ 0xFE55h USB Configuration */ 1050 1051 /* 2 USB Information (0xFE17) */ 1052 #define USB_IS_HIGH_SPEED 0 1053 #define USB_IS_FULL_SPEED 1 1054 #define USB_SPEED_MASK BIT(5) 1055 1056 #define USB_NORMAL_SIE_EP_MASK 0xF 1057 #define USB_NORMAL_SIE_EP_SHIFT 4 1058 1059 /* 2 Special Option */ 1060 #define USB_AGG_EN BIT(3) 1061 1062 /* 0; Use interrupt endpoint to upload interrupt pkt */ 1063 /* 1; Use bulk endpoint to upload interrupt pkt, */ 1064 #define INT_BULK_SEL BIT(4) 1065 1066 /* 2REG_C2HEVT_CLEAR */ 1067 /* Set by driver and notify FW that the driver has read 1068 * the C2H command message */ 1069 #define C2H_EVT_HOST_CLOSE 0x00 1070 /* Set by FW indicating that FW had set the C2H command 1071 * message and it's not yet read by driver. */ 1072 #define C2H_EVT_FW_CLOSE 0xFF 1073 1074 /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ 1075 /* Enable GPIO[9] as WiFi HW PDn source */ 1076 #define WL_HWPDN_EN BIT(0) 1077 /* WiFi HW PDn polarity control */ 1078 #define WL_HWPDN_SL BIT(1) 1079 /* WiFi function enable */ 1080 #define WL_FUNC_EN BIT(2) 1081 /* Enable GPIO[9] as WiFi RF HW PDn source */ 1082 #define WL_HWROF_EN BIT(3) 1083 /* Enable GPIO[11] as BT HW PDn source */ 1084 #define BT_HWPDN_EN BIT(16) 1085 /* BT HW PDn polarity control */ 1086 #define BT_HWPDN_SL BIT(17) 1087 /* BT function enable */ 1088 #define BT_FUNC_EN BIT(18) 1089 /* Enable GPIO[11] as BT/GPS RF HW PDn source */ 1090 #define BT_HWROF_EN BIT(19) 1091 /* Enable GPIO[10] as GPS HW PDn source */ 1092 #define GPS_HWPDN_EN BIT(20) 1093 /* GPS HW PDn polarity control */ 1094 #define GPS_HWPDN_SL BIT(21) 1095 /* GPS function enable */ 1096 #define GPS_FUNC_EN BIT(22) 1097 1098 /* 3 REG_LIFECTRL_CTRL */ 1099 #define HAL92C_EN_PKT_LIFE_TIME_BK BIT(3) 1100 #define HAL92C_EN_PKT_LIFE_TIME_BE BIT(2) 1101 #define HAL92C_EN_PKT_LIFE_TIME_VI BIT(1) 1102 #define HAL92C_EN_PKT_LIFE_TIME_VO BIT(0) 1103 1104 #define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us */ 1105 1106 /* General definitions */ 1107 #define LAST_ENTRY_OF_TX_PKT_BUFFER 176 /* 22k 22528 bytes */ 1108 1109 #define POLLING_LLT_THRESHOLD 20 1110 #define POLLING_READY_TIMEOUT_COUNT 1000 1111 /* GPIO BIT */ 1112 #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1113 1114 /* 8192C EEPROM/EFUSE share register definition. */ 1115 1116 /* EEPROM/Efuse PG Offset for 88EE/88EU/88ES */ 1117 #define EEPROM_TX_PWR_INX_88E 0x10 1118 1119 #define EEPROM_ChannelPlan_88E 0xB8 1120 #define EEPROM_XTAL_88E 0xB9 1121 #define EEPROM_THERMAL_METER_88E 0xBA 1122 #define EEPROM_IQK_LCK_88E 0xBB 1123 1124 #define EEPROM_RF_BOARD_OPTION_88E 0xC1 1125 #define EEPROM_RF_FEATURE_OPTION_88E 0xC2 1126 #define EEPROM_RF_ANTENNA_OPT_88E 0xC9 1127 1128 /* RTL88EU */ 1129 #define EEPROM_MAC_ADDR_88EU 0xD7 1130 #define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 1131 1132 /* RTL88ES */ 1133 #define EEPROM_MAC_ADDR_88ES 0x11A 1134 1135 #define EEPROM_Default_CrystalCap_88E 0x20 1136 #define EEPROM_Default_ThermalMeter_88E 0x18 1137 1138 /* New EFUSE deafult value */ 1139 #define EEPROM_DEFAULT_24G_INDEX 0x2D 1140 #define EEPROM_DEFAULT_24G_HT20_DIFF 0X02 1141 #define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04 1142 1143 #define EEPROM_DEFAULT_DIFF 0XFE 1144 #define EEPROM_DEFAULT_BOARD_OPTION 0x00 1145 1146 #define EEPROM_CHANNEL_PLAN_FCC 0x0 1147 #define EEPROM_CHANNEL_PLAN_IC 0x1 1148 #define EEPROM_CHANNEL_PLAN_ETSI 0x2 1149 #define EEPROM_CHANNEL_PLAN_SPA 0x3 1150 #define EEPROM_CHANNEL_PLAN_FRANCE 0x4 1151 #define EEPROM_CHANNEL_PLAN_MKK 0x5 1152 #define EEPROM_CHANNEL_PLAN_MKK1 0x6 1153 #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 1154 #define EEPROM_CHANNEL_PLAN_TELEC 0x8 1155 #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMA 0x9 1156 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 1157 #define EEPROM_CHANNEL_PLAN_NCC 0xB 1158 #define EEPROM_USB_OPTIONAL1 0xE 1159 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 1160 1161 #define RTL_EEPROM_ID 0x8129 1162 1163 #endif /* __RTL8188E_SPEC_H__ */ 1164