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Searched refs:CLK_VPP0_WARP1_RELAY (Results 1 – 2 of 2) sorted by relevance

/linux-6.1.9/drivers/clk/mediatek/
Dclk-mt8195-vpp0.c85 GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "top_wpe_vpp", 2),
/linux-6.1.9/include/dt-bindings/clock/
Dmt8195-clk.h473 #define CLK_VPP0_WARP1_RELAY 40 macro