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Searched refs:CLK_SCLK_UART3 (Results 1 – 15 of 15) sorted by relevance

/linux-6.1.9/include/dt-bindings/clock/
Dexynos5410.h25 #define CLK_SCLK_UART3 131 macro
Dexynos5250.h46 #define CLK_SCLK_UART3 149 macro
Dexynos7-clk.h40 #define CLK_SCLK_UART3 6 macro
Dexynos5420.h32 #define CLK_SCLK_UART3 131 macro
Dexynos4.h67 #define CLK_SCLK_UART3 154 macro
/linux-6.1.9/drivers/clk/samsung/
Dclk-exynos5410.c218 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
Dclk-exynos5250.c497 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
Dclk-exynos7.c359 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
Dclk-exynos4.c783 GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12,
Dclk-exynos5420.c985 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
/linux-6.1.9/arch/arm/boot/dts/
Dexynos5410.dtsi361 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
Dexynos4.dtsi486 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
Dexynos5250.dtsi1214 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
Dexynos5420.dtsi1337 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
/linux-6.1.9/arch/arm64/boot/dts/exynos/
Dexynos7.dtsi222 <&clock_top0 CLK_SCLK_UART3>,