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Searched refs:CLK_SCLK_MMC0 (Results 1 – 22 of 22) sorted by relevance

/linux-6.1.9/include/dt-bindings/clock/
Dexynos5410.h26 #define CLK_SCLK_MMC0 132 macro
Dexynos5250.h36 #define CLK_SCLK_MMC0 139 macro
Dexynos7-clk.h61 #define CLK_SCLK_MMC0 8 macro
Dexynos5420.h33 #define CLK_SCLK_MMC0 132 macro
Dexynos4.h58 #define CLK_SCLK_MMC0 145 macro
Dexynos3250.h249 #define CLK_SCLK_MMC0 241 macro
Dexynos5433.h570 #define CLK_SCLK_MMC0 63 macro
/linux-6.1.9/Documentation/devicetree/bindings/mmc/
Dsamsung,s3c6410-sdhci.yaml74 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
/linux-6.1.9/drivers/clk/samsung/
Dclk-exynos5410.c172 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
Dclk-exynos5250.c475 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
Dclk-exynos3250.c550 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
Dclk-exynos7.c534 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
Dclk-exynos4.c767 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
Dclk-exynos5420.c1006 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
Dclk-exynos5433.c2319 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
/linux-6.1.9/arch/arm/boot/dts/
Dexynos5410.dtsi132 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
Dexynos3250.dtsi383 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
Dexynos4.dtsi323 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
Dexynos5250.dtsi546 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
Dexynos5420.dtsi210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
/linux-6.1.9/arch/arm64/boot/dts/exynos/
Dexynos7.dtsi578 <&clock_top1 CLK_SCLK_MMC0>;
Dexynos5433.dtsi1830 <&cmu_fsys CLK_SCLK_MMC0>;