Searched refs:CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK (Results 1 – 3 of 3) sorted by relevance
616 #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109 macro
1750 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;1775 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
2303 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,