Searched refs:CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 (Results 1 – 3 of 3) sorted by relevance
750 #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96 macro
1033 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
2848 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",